10c17fdf17
Read misa before using it to check for extensions.
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Change-Id: I7a172d83055d8bd833e3349a5b22b47dd5f31f5c
2017-12-19 10:41:48 -08:00
ec1c814017
Don't rely on hart count until it's correct.
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Change-Id: I4e05eb091823b2e0fb481ca0b599072ba1ca70f2
2017-12-19 10:41:48 -08:00
46715c7d8a
Remove no-longer-true comment.
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Change-Id: I888680e73682582438a0de0496238867f1604754
2017-12-19 10:41:48 -08:00
120477b2a2
Simplify examine()
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Now we don't have to play tricks fooling other parts of our code that
might assert.
Change-Id: Ia574378e1f95ed62d297e6b2e852245e58c9ffc9
2017-12-19 10:41:48 -08:00
37278cf2ec
Make priv register 8 bits.
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(It's really only 2 bits, but something wonky happens between gdb and
OpenOCD if I make it that size.)
Change-Id: I562a65cb0ebe5aa0edcc54c251d0fea0e26f9cb1
2017-12-19 10:41:48 -08:00
f341db9f72
WIP xml register for 0.11.
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On HiFive1, FPRs show up with no name, and misa is 0x1105 instead of
0x40001105.
Change-Id: I4ee223c905ad7d860147014e7b6394668658c6ea
2017-12-19 10:41:48 -08:00
8926e66d3a
Hide unknown registers, which probably don't exist
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Change-Id: Iffa8fa5ff4b0a01abd30fa302b7087e2011337bf
2017-12-19 10:41:48 -08:00
26a54452d2
Fix register names.
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Use the ABI ones for every register that we have one for.
Change-Id: I2a993abff416d2652dbe026b3fb498e144a5006f
2017-12-19 10:41:48 -08:00
7c989698a1
WIP better CSR names, and include only existing
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Change-Id: I1a234ee07c417ba56da10a61fc2bdbdcc60490a8
2017-12-19 10:41:48 -08:00
a5cb0b2270
WIP. Hide FPRs if the hart doesn't support F/D.
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Change-Id: I988c0c36f2de8157d76874a697b3c054773b787d
2017-12-19 10:41:48 -08:00
e648856a41
`make all` debug tests now pass.
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Also properly support (I think) D extension on RV32.
Change-Id: I2f0162d36e4c18c251f99b6943403cef30d17d29
2017-12-19 10:41:48 -08:00
c421fefdcb
Checkpoint that seems to work.
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Change-Id: I9599aacc256f6340795097732b6f8e8869c2099f
2017-12-19 10:41:48 -08:00
6aff46adcc
Fix cut and paste bug.
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Now reading 64-bit FPRs on 32-bit harts using scratch memory might work.
Change-Id: Ie8c0fc689386c6e724ecab5e8c855e725fa8dd97
2017-12-14 13:51:13 -08:00
0a65a6527d
Fix build.
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Change-Id: I4e3a36fac77fefa271ae9facbaa990fa330501ae
2017-12-11 12:58:20 -08:00
e50ee46a6f
Merge pull request #131 from riscv/small_progbuf
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Support program buffers that are just 2 instructions large
2017-12-11 12:52:31 -08:00
4d5f74fbe6
Update encoding.h.
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Change-Id: Id653500aa525746e8824ff5fd2850c62c8c21c08
2017-11-27 13:23:33 -08:00
52cdf286ca
Add missing return.
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Change-Id: Ida32482903cdfd8eeb043088e84bb1f4f5ac673c
2017-11-16 15:58:08 -08:00
9b4628c9fc
Merge pull request #127 from riscv/jtag_debug
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Clean up this JTAG debug code.
2017-11-14 09:59:25 -08:00
e28abf7c9e
Merge branch 'riscv' into small_progbuf
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Change-Id: I1d48cb1f8448ebbf98c8bb369928d1e7a7a78c75
2017-11-01 13:38:17 -07:00
6a1690d2ec
Fix compile warning with new gcc.
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Change-Id: I14ebf597f41429c0fc3ebac8da9c9f62c78fb1ae
2017-10-27 13:42:39 -07:00
db754536e8
Support 64-bit FPRs on RV32.
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Because there is no instruction that moves just half of a 64-bit FPR
to/from a GPR, we need to use scratch memory for this operation. This
code can theoretically use:
1. DMI_DATA, if it is memory mapped in the target.
2. DMI_PROGBUF, if it is writable in the target.
3. A user-configured address.
I have only tested this code very lightly. One reason is that gdb thinks
that on RV32 harts every register is 32 bits wide. Another is that this
is mostly proof-of-concept to satisfy the small program buffer code
review, which I don't want to drag out forever.
Existing tests don't realize that floating support was broken with
RV32D, and don't realize that it still doesn't work because of the gdb
problem mentioned above.
This change improves Issue #110 but there's more work to be done.
Change-Id: I99b8a36e5fea26f1d9e16e36cf99adc7be26b944
2017-10-27 13:15:22 -07:00
1acb128290
Remove unused variables.
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Change-Id: I678d0a65c22792895375dc6916381f81af8f83e4
2017-10-25 13:37:56 -07:00
23bd6d08c9
Remove more unused functionality.
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Change-Id: I43283b9556c959f891a587fb39bdd1ab9206e8af
2017-10-24 15:11:33 -07:00
dbecbfee99
Add a fence after memory writes.
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Change-Id: I5137479b685f735aa573cec5d40170016c40f597
2017-10-24 12:15:25 -07:00
59a0340261
Remove more unused code.
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Change-Id: I962660f58d948f85df6e073065e15e5d8f4a02b6
2017-10-24 11:38:39 -07:00
8432b7cf3d
Remove more unused code.
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Change-Id: Id91237c163d86e8f4d039503ca33b4ad7571ecd1
2017-10-24 11:34:48 -07:00
3ba6d46fc2
Remove unused functionality.
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Change-Id: Ic70cebd62bbd04f7ae5566504fbb279a11de57f0
2017-10-23 14:45:58 -07:00
5425c871c9
Properly fix memory read when encountering busy.
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Change-Id: I377054495e860076edc2f38d1cc0f11c23f98d3b
2017-10-23 14:13:46 -07:00
a3a137062d
Pay attention to impebreak.
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This required updating debug_defines.h, which caused a few other small
cleanups as well.
Change-Id: I3c2cb418d7eff3093d7664c5563b2af5e8b530eb
2017-10-18 14:21:23 -07:00
85bfab36ad
Remove unused functionality.
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Change-Id: I0c1464e2e6aa12d0cb1025ed0a7c1c483e7403b7
2017-10-18 12:47:07 -07:00
5d3f5c35d2
Still restore registers if an access failed.
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Change-Id: I11571f0926f69a34f95b4929f633fdecd3a4e810
2017-10-18 12:32:41 -07:00
7edd9b1786
Fix FPR access.
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Change-Id: I1379de87904f1cf40b45d1a5490249e3ba90d7d0
2017-10-18 11:47:15 -07:00
a0623b2fa8
Don't crash when encountering RV64.
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Change-Id: Ie915ce830c3499919e4918ad443a5e225cf8c4d9
2017-10-17 11:58:51 -07:00
65be0776d8
Memory read/write works if the core can keep up.
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Change-Id: Ieca50ece266fbc9d2ff16a5cc2e6b4b926ad5e6f
2017-10-17 11:52:07 -07:00
fbe2980eb7
MemTest64 passes.
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Change-Id: I75996b71c3f31025c89ef596a08e01d191405336
2017-10-17 11:15:51 -07:00
d94b38279a
Memtest{16,32} pass.
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Change-Id: I15c2a4fd2bb9a7b30762d07f3b3a74d2f477746b
2017-10-16 21:08:59 -07:00
7ec7bc32fe
At least some memory writes work.
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Change-Id: I6fcf261341f10ec34df01bb844744439d02471a8
2017-10-13 12:50:02 -07:00
e7bb815e87
Register read/write might be working.
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Change-Id: I6c51d6157dde56d8cd666b4d30ec7bbc7a4bef9f
2017-10-12 14:38:52 -07:00
94e8250713
WIP; doesn't work.
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Change-Id: Ia407e82ccbd2044ad61e0845d285dd5765154476
2017-10-12 11:45:52 -07:00
77802af655
Remove duplicate progbuf size variable.
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Change-Id: I662ff84d13ecfc7faae51406a4df57a3643116f0
2017-10-10 16:27:51 -07:00
f06aaa9058
Merge pull request #123 from riscv/fast_rbb
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Add read buffer to bitbang, improving performance.
2017-10-09 11:06:20 -07:00
2da7820833
Revert this LOG_INFO to LOG_DEBUG.
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Change-Id: I75dd7667a542aa1c6ea10f97fe1e00dd1ecba69d
2017-10-08 11:41:55 -07:00
7aafd61953
Clean up this JTAG debug code.
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Change-Id: Ie7c773b98271d11085d5e50c40b64990710de387
2017-10-06 13:55:52 -07:00
d5836dceff
Merge pull request #126 from riscv/compile
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Fix compile warnings.
2017-10-04 16:07:40 -07:00
24658db50e
Fix compile warnings.
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Partly fixes #124 .
Change-Id: I3a7fd65c643e40b142709806cb9fb4cc62bb955f
2017-10-04 16:02:30 -07:00
916759e0de
Revert ae74097f (extra ftdi debug).
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Instead it makes more sense to push the debug changes to jtag/core.c.
Change-Id: I73bafa2a054e1f72b7752cfbce9ffc14303fc4c4
2017-10-04 15:44:07 -07:00
28eb10f43d
Ensure the buffer doesn't overflow.
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Tested with a variety of prime buffer sizes.
Change-Id: I2b4835d46adf4c971111da88e8de4b46eb8dad41
2017-10-04 15:23:38 -07:00
abe7eba25a
Merge pull request #118 from riscv/priv
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Fix priv access
2017-10-04 12:52:21 -07:00
1b11d579ea
Add read buffer to bitbang, improving performance.
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This reduces the time for one testcase where OpenOCD connects to a
simulator from 12.30s to 5.35s!
Running all our tests went from 13m13s to 3m55s.
Change-Id: I7dc774e1e0f5752905ac4318fd9b85b930374a05
2017-10-03 15:38:31 -07:00
a3c26250bf
Merge pull request #116 from riscv/multigdb
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Fix trigger code to work with multi-gdb mode instead of RTOS mode
2017-10-03 11:53:58 -07:00
Tim Newsome