This makes it easier to relocate the install tree of OpenOCD from where
it was originally built (for example, if put onto a different machine),
without having to change scripts or add something to the command line
every time.
Change-Id: Ia5edf0eba166f7a999f267bd6a92402dab9b399e
Signed-off-by: Jonathan Larmour <jifl@eCosCentric.com>
Reviewed-on: http://openocd.zylin.com/3004
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add configs for Atheros ar2313 MIPS based WiSoC and
board based on this chip: La Fonera FON2200
Change-Id: Ibfdbfc9c2beca6cf436c9ee5e493b08bfb55ac85
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2839
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add configs for Atheros ar2313 MIPS based WiSoC and
board based on this chip: Netgear WP102
Change-Id: Id93957b5d5851a272f15be35f9f448a9ce6d8a08
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2835
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The memory leak occurs when opening a file fails. It can be
reproduced by using the "flash verify_bank" command with a filename
that does not exist.
Change-Id: I60b7b545c18793d750ff75d08124fde3f0aa6f64
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/2998
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
If we work on smp system, the output of step command will depend
on Id of default target.
This patch adds additional information to help find what on which
core is happening.
Example of LOG after this patch.
imx6.cpu.1: target state: halted
^^^^^^^^^^
target halted in ARM state due to breakpoint, current mode: Supervisor
cpsr: 0x60000093 pc: 0x80076c0c
MMU: enabled, D-Cache: enabled, I-Cache: enabled
imx6.cpu.0: target state: halted
^^^^^^^^^^
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x20000193 pc: 0x802ccb6c
MMU: enabled, D-Cache: enabled, I-Cache: enabled
Change-Id: I536a2cce33b5ab10af9de2a43b9960320c17729f
Signed-off-by: Oleksij Rempel <external.Oleksij.Rempel@de.bosch.com>
Reviewed-on: http://openocd.zylin.com/2691
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
A segmentation fault in cortex_m_endreset_event() is sometimes raised
with very broken target like Kinetis Kx with erased flash and active WDOG.
Debugging revealed that cortex_m->dwt_num_comp is 4 and
dwt_list is NULL at cortex_m:290
Change-Id: I229c59d6da13d816df513d1dbb19968e4b5951e2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2989
Reviewed-by: Thomas Schmid <thomas@rfranging.com>
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Since 2cbbe9a it was actually decreasing the configured work area size.
We could now do "set WORKAREASIZE 0x2000" before sourcing lpc4350.cfg,
but there seems no point in doing so. Simply drop the configuration here.
Change-Id: I25b9dbbc007ba652b66099832198b7c329929858
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3086
Tested-by: jenkins
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Memory for the symbol table was allocated by malloc but not initialized other
than with the symbol name. Therefore `address` and `optional` members were
having arbitrary values leading to every symbol being optional most of the
time which messes up RTOS auto-detection. Memory will now be zero-initialized
as in other RTOS implementations.
Change-Id: I6c6e31ec1ef7e043061adf8c695b2139620e005d
Signed-off-by: Daniel Krebs <github@daniel-krebs.net>
Reviewed-on: http://openocd.zylin.com/3017
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Default to lpc8xx as before, but allow setting the actual CHIPNAME.
Change-Id: I5a48fa75c640440a0d4c3f2858653e94bed846d2
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3084
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
According to "man 2 poll" the correct header to include is poll.h, not
sys/poll.h. Reported by a build against musl.
Change-Id: I5298b49dc947d1a368e423104c0c0c7b9bdd1a10
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2947
Tested-by: jenkins
Board files should not select the interface. The BeagleBone Black is not
limited to just one JTAG interface.
Change-Id: I71ccc3dd9e2ca331a436701fab04e548b0abf829
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3083
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
In the case that the STKALIGN bit is set on Cortex M processors, on
entry to an exception - the processor can store an additional 4 bytes
of padding before regular stacking to achieve 8-byte alignment on
exception entry. In the case that this padding is present, the
processor will set bit (1 << 9) in the stacked xPSR register. Use the
new calculate_process_stack callback to take into account the xPSR
register and use it on the standard Cortex_M3 stacking.
Note: Change #2301 had some misinformation regarding the padding. On
Cortex-M the padding is stored BEFORE stacking so xPSR is always
available at a fixed offset.
Tested on a Cortex-M0+ (Atmel SAMR21) board which has STKALIGN fixed
to a '1' such that this alignment always occurs on non-aligned stacks.
Behavior of xPSR verified via the (bad-sorry) assembly program below by
setting a breakpoint on the SVC_Handler symbol. The first time
SVC_Handler is triggered the stack was 0x20000ff8, the second time
SVC_Handler is triggered the stack was 0x20000ffc. Note that in both
cases the interrupt handler gets 0x20000fd8 for a stack pointer.
GDB exerpt:
Breakpoint 1, 0x000040b6 in Reset_Handler ()
(gdb) hbreak SVC_Handler
Hardware assisted breakpoint 2 at 0x40f8
(gdb) cont
Continuing.
Breakpoint 2, 0x000040f8 in SVC_Handler ()
(gdb) print $msp
$3 = (void *) 0x20000fd8
(gdb) x/9w $msp
0x20000fd8: 0x1 0x2 0x3 0x4
0x20000fe8: 0x88160082 0xa53 0x40ce 0x21000000
0x20000ff8: 0x0
(gdb) cont
Continuing.
Breakpoint 2, 0x000040f8 in SVC_Handler ()
(gdb) print $msp
$4 = (void *) 0x20000fd8
(gdb) x/9w $msp
0x20000fd8: 0x1 0x2 0x3 0x4
0x20000fe8: 0x88160082 0xa53 0x40e8 0x21000200
0x20000ff8: 0x0
Assembly program:
.cpu cortex-m0plus
.fpu softvfp
.thumb
.syntax unified
.section .vectors
@ pvStack:
.word 0x20001000
@ pfnReset_Handler:
.word Reset_Handler + 1
@ pfnNMI_Handler:
.word 0
@ pfnHardFault_Handler:
.word 0
@ pfnReservedM12:
.word 0
@ pfnReservedM11:
.word 0
@ pfnReservedM10:
.word 0
@ pfnReservedM9:
.word 0
@ pfnReservedM8:
.word 0
@ pfnReservedM7:
.word 0
@ pfnReservedM6:
.word 0
@ pfnSVC_Handler:
.word SVC_Handler + 1
.section .text
.global Reset_Handler
Reset_Handler:
cpsie i
ldr r0, .stack_start
ldr r2, .stack_last
eors r1, r1
.loop_clear:
str r1, [r0]
adds r0, r0, #4
cmp r0, r2
bne .loop_clear
subs r2, r2, #4
mov sp, r2
movs r0, #1
movs r1, #2
movs r2, #3
movs r3, #4
svc #0
ldr r0, .stack_start
ldr r2, .stack_last
eors r1, r1
.loop_clear2:
str r1, [r0]
adds r0, r0, #4
cmp r0, r2
bne .loop_clear2
mov sp, r2
movs r0, #1
movs r1, #2
movs r2, #3
movs r3, #4
svc #0
.loop:
b .loop
.align 4
.stack_start:
.word 0x20000f00
.stack_last:
.word 0x20000ffc
@ first call - 0x2000fff8 -- should already be aligned
@ second call - 0x2000fffc -- should hit the alignment code
.global SVC_Handler
SVC_Handler:
bx lr
Change-Id: Id0940e6bbd6a59adee1378c0e86fe86830f0c8fc
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Paul Fertser <fercerpav@gmail.com>
Cc: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Cc: Evan Hunter <evanhunter920@gmail.com>
Cc: Jon Burgess <jburgess777@gmail.com>
Reviewed-on: http://openocd.zylin.com/3003
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Some targets (Cortex M) require more complicated calculations for
turning the stored stack pointer back into a process stack pointer.
For example, the Cortex M stores a bit in the auto-stacked xPSR
indicating that alignment had to be performed and an additional 4
byte padding is present before the exception stacking. This change
only sets up the framework for Cortex-M unstacking and does not
add Cortex-M support.
Note: this also fixes the alignment calculation nearly addressed by
change #2301 entitled rtos/rtos.c: fix stack alignment calculation.
Updated calculation is in rtos_generic_stack_align.
Change-Id: I0f662cad0df81cbe5866219ad0fef980dcb3e44f
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Paul Fertser <fercerpav@gmail.com>
Cc: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Cc: Evan Hunter <evanhunter920@gmail.com>
Cc: Jon Burgess <jburgess777@gmail.com>
Reviewed-on: http://openocd.zylin.com/3002
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
Intel is relicensing our contributions to OpenOCD under GPL
version 2 or any later version. We previously contributed code
under GPL version 2 only. It was not our intention to differ
from the standard OpenOCD license. We're correcting that here.
This also applies retroactively to previous versions of our
contributions to OpenOCD.
Change-Id: I5e831ed95d03d2044d8e5a8375b21c6e52c933d7
Signed-off-by: Ivan De Cesaris <ivan.de.cesaris@intel.com>
Reviewed-on: http://openocd.zylin.com/3044
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Adapted from diolan_lpc4350-db1.cfg. Both boards are identical except
for the SoC, so keep them in sync.
Change-Id: If892d8e953b0e3a9209a95b3b23a547357c10b7a
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3038
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reuse the flashless LPC4350 as base and amend it as necessary.
The LPC43x7 have 2x 512 KB of flash.
Change-Id: Ia7ffbc7101023479971984b839f171ed4be6b089
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3037
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
fm3, nrf51, mdr, sim3x were at the end of the section rather than
inserted alphabetically. Fix this before adding further drivers.
Change-Id: Id23e04749cdd3b25d7503ec00fac554742d48c77
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3019
Tested-by: jenkins
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add support for the JTAG TAPID found on SK-FM4-U120-9B560-MEM V1.1.0 board.
Change-Id: Idbfe28927e0c549f0c89c29904d23971281927c9
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3039
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
It is found on the SK-FM4-U120-9B560-MEM V1.1.0 among others.
Change-Id: I4c708c9391e954cbbc8d0860a2a2dbd264aea865
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3008
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Its memory layout is different from MB9BFxxx.
Change-Id: I39c9f9cf582cd182971a9f83bb88c7a18da6cf15
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3007
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The xCORE-XA Core Module board has an XS1-XAU8A-10 SoC with 8 xCORE cores
and one ARM core. This config is for the ARM Cortex-M3, via J-Link OB.
Tested with "J-Link OB-STM32F103 V1 compiled Feb 5 2014 13:48:52".
Change-Id: Id7fadf8f323b45d5cfc0cae1054bd7b916771d6a
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2763
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The XS1-XAU8A-10 has 8 xCORE cores and one ARM core.
This config represents the ARM Cortex-M3 core, which is apparently
Silicon Labs EFM32 Giant Gecko IP.
Change-Id: I998360f096c759d2e274d96c1ca2e0450ba61146
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2762
Tested-by: jenkins
Reviewed-by: Oleksij Rempel
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Most Xilinx FPGA devices contain an embedded, unique device identifier
called the "Device DNA". The identifier is nonvolatile, permanently
programmed into the FPGA, and is unchangeable providing a great serial
/ tracking number.
Debugging was done in https://github.com/timvideos/HDMI2USB/issues/36
Change-Id: Iad03eafb40887f0321a4dc22858a7c3bf37a12b3
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Reviewed-on: http://openocd.zylin.com/2960
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Another board supported by the ixo-usb-jtag project.
Change-Id: I676197c64e208886bc03d1bafcc964ef1fc2160b
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Reviewed-on: http://openocd.zylin.com/2963
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The board is supported via the ixo-usb-jtag firmware.
Change-Id: I1e8a5ead850c0843b8532a5b54a7e7117778278e
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Reviewed-on: http://openocd.zylin.com/2962
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Also add further documentation about the project and how to use it.
Change-Id: Ia9878de566b3c8c1ea29f129287d5aea904d861d
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Reviewed-on: http://openocd.zylin.com/2961
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
K22FN1M0 and K22FX512 has FTFE flash and old style SDID.
K22FN128, 256 and 512 has FTFA flash and new style SDID
K63 and K64 detects as K61 and K62, see Errata 1N83J e7534
Change-Id: I2aca6f1f18819bb2b2ec4982036510de444ad2ac
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2867
Tested-by: jenkins
Reviewed-by: Thomas Schmid <thomas@rfranging.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Patrick Stewart <patstew@gmail.com>
max_flash_prog_size euals to pflash_sector_size_bytes for most of devices.
There is no point setting max_flash_prog_size for devices without
FS_PROGRAM_SECTOR capability.
Check for zero sector_size to avoid div by zero exception in case of
device has FlexNVM but the driver does not define nvm_sector_size_bytes
Change-Id: Iaf4e007fb1ec3d24c373350410e4bebe504a4c3e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2958
Tested-by: jenkins
Reviewed-by: Thomas Schmid <thomas@rfranging.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Patrick Stewart <patstew@gmail.com>
The K24 uses the KL-style SDID register and has some flashing quirks, so the kinetis driver does not support it properly.
Extend the chip detection routine to support the new SDID format. Add a parameter for the maximum flash size, as the K24 only supports 1k flashing blocks but has 4k sector size. Remove global 'granularity' array, as it's only really needed in one function. Replace 'klxx' with an enum showing which flash commands are actually supported on a given chip.
Signed-off-by: Patrick Stewart <patstew@gmail.com>
Change-Id: Ie244fab564d58c5cfe4fa36a025f0b2674ffad69
Reviewed-on: http://openocd.zylin.com/2864
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Change-Id: I3cf5ced568319878b8bf40743e4c07718f630c68
Signed-off-by: Jim Paris <jim@jtan.com>
Reviewed-on: http://openocd.zylin.com/2953
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Jonathan Larmour
Oleksij Rempel
Marc Schink
Oleksij Rempel
Tomas Vanek
Andreas Färber
daniel-k
Paul Fertser
Maxime Coquelin
Maxime Coquelin
Matthias Welwarsky
Andrew Ruder
Uwe Bonnes
Ivan De Cesaris
fenugrec
Forest Crossman
Tim 'mithro' Ansell
Peter A. Bigot
Patrick Stewart
Alex Forencich
Evan Hunter
Jim Paris