* Add flexible selection of memory access methods, detection of aampostincrement.
New configuration command introduced: "riscv set_mem_access".
It allows to specify which RISC-V memory access methods (progbuf,
sysbus and/or abstract access) should be tried and in which order
of priority.
Command "riscv set_prefer_sba" is left and works in backward
compatible way, but is marked as deprecated.
First time abstract memory access is executed, it is tried with
set aampostincrement bit. If the abstract command fails or the
address is not incremented correctly, aampostincrement will not
be used for any subsequent accesses.
Signed-off-by: Samuel Obuch <sobuch@codasip.com>
* remove unnecessary variable
* fix doc
* Backport of GD32VF103 flash driver from https://github.com/riscv-mcu/riscv-openocd (GPL2 licensed)
Tested with a "Longan Nano" GD32VF103 dev board and seems to be working (flash can be read, erased and written).
* Modify src/flash/nor/gd32vf103.c to comply with Travis CI code style requirements.
* Modified README to include GD32VF103 in list of supported flash devices.
* Make checkpatch require Signed-off-by
This will make it easier to send changes contributed here to mainline
OpenOCD.
(Intentionally not including the required line here to make sure I can't
just merge this.)
Change-Id: I089084d38f3e08859d62cf7eface405f37af4799
* Whitespace fix.
This PR isn't building on travis. Maybe because I only changed
.travis.yml. Here's a source change to force a build (hopefully).
Change-Id: I8a828fe1d56a1960bc4bfb91d3d2f3a0790ad571
* Can't check for signoff on sources alone.
Change-Id: I741a299b64bf14857a4e1807b254a7d270b2e466
Signed-off-by: Tim Newsome <tim@sifive.com>
* Actual whitespace fixes.
Why didn't this fail to build before?
Change-Id: I339c03c4ef96546dbef5f16e635921a4fdaf9b35
Signed-off-by: Tim Newsome <tim@sifive.com>
A ton of constants got a new prefix, so I made a lot of changes to
match, but no functional changes.
I did define DTM_DMI_MAX_ADDRESS_LENGTH in batch.c. That definition
never should have been in debug_defines.h, which I missed during code
review.
Change-Id: If5d86660f84bb0a3f2865fb36ef05d6630486d8b
Accessing registers on targets that implement 0.9 or earlier will no
longer work. If you need that we can talk about making it a config
option.
Change-Id: I953b639cf9a92ee9b0422e035da57c1d07504237
* WIP, apply stash with conflicts.
Change-Id: Ia794bde419aa29161c68898d20e30527e69f5a31
* Fix conflict resolution problems.
Change-Id: I4cedc348cf613f98cc5a36886f37c568ca644238
* Add repeat_read command.
Only implemented for sba v1 right now, and poorly tested at that.
Change-Id: I1d9ff63e1dea14b3f6a9f8ba4dad53668bf8038b
* Hide bogus address in repeat_read
Change-Id: Ib66c1fa60df9c7fc7cc87880b0fddc52825b48aa
* WIP make repeat read work with progbuf.
Change-Id: I555f8b880c8bf0d1ed0f3f90c7987a5b516a7a79
* WIP
Change-Id: Ic567cea68355ae907e94bd25185a2c9be6fd798d
* Fix error handling when increment is non-zero.
Change-Id: I5a2f3f2ee948fd4e12c0443a542e85b7b5c5791a
* Correctly(?) handle failures when increment is 0.
I'm not 100% convinced that this ensures every read value shows up in
the output, but it ought to work.
Change-Id: I1af3e7174cf9d5e6f293456fb5ead629e17faaaa
* Don't crash when asked to read no data.
Change-Id: I4061b5c720a43a4f828384ab9eacc89557adfa05
* Remove unnecessary comment.
Change-Id: I1be3d699b86299339b3a830ca1ef13c9f5b9fe0f
* Document `riscv repeat_read`.
Change-Id: I4a0f071f38784b2de034f8c1b0ce75d6d2d326b2
* Further deprecate `-rtos riscv`.
Now using `-rtos riscv` will result in a failure, which you can (until
the end of this year) bypass by adding `enable_rtos_riscv` to the
configuration.
Change-Id: Ic714c303dc1b00c19e8956609730c0f83c845cb6
* Make checkpatch happy.
Change-Id: I0469ec37d38ad2eadf25efb5b2b7ac88391c0f51
Technically that might be OK, but in practice it probably indicates
something went wrong somewhere. Before this change OpenOCD would crash
if it happened.
Change-Id: I2500ba67ec282915dcf2b2488f2aac9fbfdb23a3
This logic is a little tortured, but it still passes the semihosting
tests that were the cause for the recent rewrite.
Change-Id: Ic6760bb068621ab2a49feb0cf3998fc6957b5cfc
This update is for testing the upcoming 0.2.0 release.
Change-Id: I400b09eb3ead4306c83c7980c621124101aaef7e
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/5723
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
* Accommodate users setting custom triggers.
RISC-V hardware supports many more triggers than gdb can communicate to
OpenOCD. Accommodate users that set triggers by writing tdata* directly,
by disable/step/reenable when a user has done that.
Note that users must set dmode in tdata1 for this behavior to work
properly. Triggers with dmode=0 are assumed to be set and handled by the
software that is being debugged.
Change-Id: Ib0751689c5553aae3a273395b10f5b98326fa066
* Enumerate triggers when resuming from a trigger
Otherwise when we connect to a target that's already halted due to a
trigger, we won't correctly step past it.
Change-Id: I23b9482fa9597af826770f9cebf247b7ba59f65c
* Also disable/reenable triggers around single step.
Gdb is smart enough to disable/step/resume if it set the triggers, but
if a user set them manually it also needs to happen.
Change-Id: I1251bd47199b6f15f61a93e3a521a53f2b677c5f
* Fix whitespace.
Change-Id: Icc240aecbc7e3e36ce4e4d784f5703304334ca13
This fixes a regression introduced in "2dc88e1479f29ef0141b05bfcd907ad9a3e2d54c"
Change-Id: I04dc19ed30118a4c499b83732700b2ee0fdb67b6
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/5610
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The name conflict is picked by compiler and it fails to compile for rv64
Fixes
src/target/riscv/riscv-011.c:1014:44: error: too many arguments provided to function-like macro invocation
static int read_csr(struct target *target, uint64_t *value, uint32_t csr)
^
Signed-off-by: Khem Raj <raj.khem@gmail.com>
In addition to the debug TAPs, the ICEPick C also supports
a bank of Test TAPs (limited functionality intended for
non-debuggable targets). Added support for Test TAPs to
the icepick_c_tapenable routine. Port numbers of 0 to 15
will continue to be handled as a debug TAP number. Test
TAPs will be port numbers of 16 to 31.
This functionality will be needed for doing a flash
mass erase on CC26xx/CC13xx targets. It is possible
for user application to block even adding the Cortex M
TAP to the scan chain, so the only way to unbrick the
target and erase the flash is using a component on a
test TAP of the device's ICEPick router.
Change-Id: I0aa52a08d43a00cbd396efdeadd504fc31c98510
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/5715
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The current version erroneously allows any number of arguments >= 1.
Change-Id: I64156c11b48d411c72bebbf866954818cd036ff2
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/5716
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Issue: server_quit is called before adapter_quit:
In WIN32 only in server_quit we do an WSACleanup,
which terminates/closes all active sockets.
So if the adapter is TCP based, the adapter.quit handler
will fail if it will need to send some commands through TCP.
Example: close_socket in jtag_vpi_quit will fail in WIN32
because the socket is already closed
and the errno is set as "Bad File Descriptor"
To fix that we introduced new functions called server_host_os_entry/quit
to manage specific OS setup (hence WSA for sockets in WINDOWS) in order
to delay WSACleanup after adapter_quit().
Change-Id: Ie4afacafe123857f6ae300e376bdfcf0d8c027ac
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5456
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Issue identified by checkpatch script from Linux kernel v5.1 using
the command
find src/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types MULTILINE_DEREFERENCE -f {} \;
Change-Id: Icba05613e22a72ecc3e6a0aad7cb6b479496146f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5629
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
If the function parse_u64() fails, we jump to return, thus leaking
the memory just allocated in 'v'.
Issue identified by clang.
Move earlier the call to parse_u64() and the associated test,
before memory allocation.
While there, fix a possible NULL pointer dereferencing in case the
calloc() fails, by testing for allocation failure.
Change-Id: I6a77ee17aceb282bbdfefe7cdafeba2e0e7012f1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5692
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
There is no method to free the register cache, allocated in
armv4_5, so we get a memory leak.
Issue identified by valgrind.
Implement the method arm_free_reg_cache() and call it in cortex_a
deinit and to exit for error during arm_dpm_setup().
Tested on dual cortex-A stm32mp15x.
This change is inspired from similar fix in commit b01b5fe13a
("armv7m: Fix memory leak in register caching.").
The same allocation is also used by target types "arm7tdmi",
"arm9tdmi", "arm11" and "xscale" but they all lack the deinit
method and I do not have relevant HW to test the fix. For such
reasons they are not addressed in this patch.
Change-Id: I4da1e1f12e36ec245d1f3b11a4eafcbd9a1d2e25
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5693
Tested-by: jenkins
The target mem_ap misses the method 'deinit_target' and does not
free the memory allocated during 'target create' and 'configure'.
Add the missing method and free the allocated memory.
Issue identified with valgrind.
Change-Id: If0d0114a75dd76a8b65c2d46d96c6085fd31a09d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5700
Tested-by: jenkins
When jtag_libusb_open() fails to find the adapter, it returns
error but left libusb initialized causing memory leak of libusb
internal data.
Issue found with valgrind when no adapter or board is connected to
the host, e.g.
valgrind openocd -f board/st_nucleo_f4.cfg
Close the libusb operations if jtag_libusb_open() has to return
error.
Change-Id: Ieb2f110be15705dafe80c099e7d83c07056c2a41
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5701
Tested-by: jenkins
Current code for Cortex M does not set C_DEBUGEN as soon as
possible, (which means during target examine), but later-on either:
1) at command 'halt' (e.g. for 'gdb-attach' event);
2) at command 'soft_reset_halt';
3) at commands 'reset', 'reset halt' or 'reset init';
4) during polling, but only if the target:
= enter in 'double fault', or
= exit from a reset, or
= halts (not possible if C_DEBUGEN is not set)
Plus, if commands in 1) or 2) are executed before the very first
poll of the target, the value of 'cortex_m->dcb_dhcsr' is used not
initialized while writing it back in DCB_DHCSR.
Another side effect of this situation is that it's possible to set
a HW breakpoint with the target running, while C_DEBUGEN is not
set. Accordingly to [1], C1.3.1 "Debug authentication":
When DGBEN is LOW and DHCSR.S_HALT == 0:
...
FPB breakpoints do not generate an entry to Debug state and,
if no DebugMonitor exception is generated, will escalate to
HardFault, Lockup, or be ignored.
On STM32MP15x I get HW breakpoint ignored, while on STM32F411 I
get HardFault.
E.g. following these steps:
- power-on a pre-flashed board that starts running the firmware;
- connect openocd, without halting or resetting the board;
- set a HW breakpoint to some address often executed;
- wait, but the board doesn't halt ...;
- type the command 'halt';
- if the Cortex-M has HardFault it would be visible and the fault
is at the breakpoint address;
- if no HardFault then type the command 'resume';
- wait and the board will finally halt at the HW breakpoint.
A similar issue has been detected on Cortex-A code and fixed by
commit bff87a7f28 ("target/cortex_a: enable DSCR_HALT_DBG_MODE
during examine").
Follow the same approach and set C_DEBUGEN during examine.
Also, initialize 'cortex_m->dcb_dhcsr' during examine.
[1] ARM DDI 0403E "ARM v7-M Architecture Reference Manual"
Change-Id: I5b0b23403634f7dfce38f104bba9f59c33eb3e99
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5702
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Moritz Fischer <moritzf@google.com>
The kept_alive() function is called to inform the keep-alive code
that a keep-alive as been just kicked through some other path.
But kept_alive() erroneously resets the timeout counter without
checking if it has already expired, thus masking a potential
timeout.
Check if timeout counter has expired during kept_alive().
While there, put the timeout values in macros and explicit the
units in the timeout messages.
Change-Id: Iaf6368b44e5b5352b1cc4e7efbb2368575dcfa08
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5705
Reviewed-by: <jonatan_zeidler@gmx.de>
Tested-by: jenkins
Flashing Kinetis MCU MK22FX512VLH12 takes longer than one second,
thus gdb connection can timeout. Before commit 7f260f5009
("helper/command: Handle Tcl return values consistently") the
openocd timeout warning was masked by a bug in gdb_put_packet()
that resets the timeout counter if any message is logged out.
The commit above removes one log message and the timeout warning
is now triggered.
While the bug in gdb_put_packet() is still to be fixed, the reason
of the timeout is the lack of keep_alive() calls in kinetis flash
driver.
Add keep_alive() call at every iteration in function
kinetis_write_sections(), that is reported as core write function
in chunks of 1024 bytes in the log from the reporter.
Add also a keep_alive() call at every iteration in function
kinetis_write_inner(). This part is not present in the log but, by
code analysis, it represents another critical loop.
Change-Id: I38e631b36c7eb2f1e21cef68710ce47c03d3edda
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Jonatan Hatakeyama Zeidler <jonatan.zeidler@medineering.de>
Reviewed-on: http://openocd.zylin.com/5703
Tested-by: jenkins
Reviewed-by: <jonatan_zeidler@gmx.de>
Tim Newsome
Samuel Obuch
ZL2WRW
Jiuyang Liu
Samuel Obuch
Jan Matyas
Ma_124
Yun Liu
Jaehoon Park
Marc Schink
Khem Raj
Edward Fewell
Tarek BOCHKATI
Alistair Francis
Antonio Borneo