riscv-openocd/tcl/target/str730.cfg

#STR730 CPU

jtag_khz 3000

if { [info exists CHIPNAME] } {	
   set  _CHIPNAME $CHIPNAME    
} else {	 
   set  _CHIPNAME str730
}

if { [info exists ENDIAN] } {	
   set  _ENDIAN $ENDIAN    
} else {	 
   set  _ENDIAN little
}

if { [info exists CPUTAPID] } {	
   set  _CPUTAPID $CPUTAPID    
} else {	 
   set  _CPUTAPID 0x3f0f0f0f
}

#use combined on interfaces or targets that can't set TRST/SRST separately
#reset_config trst_and_srst srst_pulls_trst
reset_config trst_and_srst srst_pulls_trst

#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID

#jtag nTRST and nSRST delay
jtag_nsrst_delay 500
jtag_ntrst_delay 500

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi

$_TARGETNAME configure -event reset-start { jtag_khz 10 }
$_TARGETNAME configure -event reset-init { jtag_khz 3000 }
$_TARGETNAME configure -event gdb-flash-erase-start {
	flash protect 0 0 7 off
}

$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0

#flash bank <driver> <base> <size> <chip_width> <bus_width>
flash bank str7x 0x20000000 0x00040000 0 0 0 STR3x