riscv-openocd/tcl/target/str750.cfg

#STR750 CPU

if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME str750
}

if { [info exists ENDIAN] } {
   set _ENDIAN $ENDIAN
} else {
   set _ENDIAN little
}

if { [info exists CPUTAPID] } {
   set _CPUTAPID $CPUTAPID
} else {
   set _CPUTAPID 0x4f1f0041
}

# jtag speed
adapter_khz 10

#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst

#jtag scan chain

jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID

#jtag nTRST and nSRST delay
adapter_nsrst_delay 500
jtag_ntrst_delay 500

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi

$_TARGETNAME configure -event reset-start { adapter_khz 10 }
$_TARGETNAME configure -event reset-init {
	adapter_khz 3000

	init_smi
# Because the hardware cannot be interrogated for the protection state
# of sectors, initialize all the sectors to be unprotected. The initial
# state is reflected by the driver, too.
	flash protect 0 0 last off
	flash protect 1 0 last off
}
$_TARGETNAME configure -event gdb-flash-erase-start {
	flash protect 0 0 7 off
	flash protect 1 0 1 off
}

$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0

#flash bank <driver> <base> <size> <chip_width> <bus_width>
set _FLASHNAME $_CHIPNAME.flash0
flash bank $_FLASHNAME str7x 0x20000000 0x00040000 0 0 $_TARGETNAME STR75x
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME str7x 0x200C0000 0x00004000 0 0 $_TARGETNAME STR75x

# Serial NOR on SMI CS0.
set _FLASHNAME $_CHIPNAME.snor
flash bank $_FLASHNAME stmsmi 0x80000000 0 0 0 $_TARGETNAME

source [find mem_helper.tcl]

proc init_smi {} {
	mmw 0x60000030 0x01000000 0x00000000; # enable clock for GPIO regs
	mmw 0xffffe420 0x00000001 0x00000000; # set SMI_EN bit
	mmw 0x90000000 0x00000001 0x00000000; # set BLOCK_EN_1
}