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ethernet
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WIP 100BASE-TX PHY
26 Commits 2 Branches 0 Tags 290 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
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Sean Anderson fec8a0a9f6 tb: pcs: Don't convert codes to list in pcs_send_codes 
This does nothing (especially since we immediately create an iterator)

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-08-08 00:11:58 -04:00
rtl pcs: rx: Only flush on state change 2022-08-06 22:08:09 -04:00
tb tb: pcs: Don't convert codes to list in pcs_send_codes 2022-08-08 00:11:58 -04:00
.gitignore Initial commit 2022-05-23 20:57:03 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Add post-synthesis simulation support 2022-08-06 21:47:21 -04:00