70 lines
1.4 KiB
Verilog
70 lines
1.4 KiB
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only
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/*
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* Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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*/
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`include "common.vh"
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`include "io.vh"
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module hub_core (
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input clk,
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/* MII */
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input [PORT_COUNT - 1:0] rx_dv,
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input [PORT_COUNT - 1:0] rx_er,
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input [PORT_COUNT * 4 - 1:0] rxd,
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output reg [PORT_COUNT - 1:0] tx_en,
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output reg [PORT_COUNT - 1:0] tx_er,
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output reg [PORT_COUNT * 4 - 1:0] txd
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);
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parameter PORT_COUNT = 4;
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localparam PORT_BITS = $clog2(PORT_COUNT);
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localparam DATA_JAM = 4'h5;
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integer i;
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reg jam, activity;
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reg [PORT_BITS - 1:0] active_port;
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reg [PORT_COUNT - 1:0] tx_en_next, tx_er_next;
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(* mem2reg *)
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reg [3:0] txd_next [PORT_COUNT - 1:0];
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always @(*) begin
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jam = 0;
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activity = 0;
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active_port = {PORT_BITS{1'bx}};
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for (i = 0; i < PORT_COUNT; i = i + 1) begin
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if (rx_dv[i]) begin
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if (activity)
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jam = 1;
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else
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active_port = i;
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activity = 1;
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end
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end
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for (i = 0; i < PORT_COUNT; i = i + 1) begin
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tx_en_next[i] = 0;
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tx_er_next[i] = rx_er[active_port];
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txd_next[i] = rxd[active_port * 4 +: 4];
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if (jam) begin
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tx_en_next[i] = 1;
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tx_er_next[i] = 0;
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txd_next[i] = DATA_JAM;
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end else if (activity && i != active_port) begin
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tx_en_next[i] = 1;
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end
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end
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end
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always @(posedge clk) begin
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tx_en <= tx_en_next;
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tx_er <= tx_er_next;
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for (i = 0; i < PORT_COUNT; i = i + 1)
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txd[i * 4 +: 4] <= txd_next[i];
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end
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endmodule
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