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WIP 100BASE-TX PHY
123 Commits 2 Branches 0 Tags 285 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
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Sean Anderson eb8d854476 Silence warnings when converting memories to registers 
There are several places where memories are used for parametrization
purposes, but I intend them to be synthesized to registers. Silence
warnings about them by explicitly annotating these variables.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2023-02-18 22:48:36 -05:00
LICENSES Add LFSR 2023-01-09 21:01:27 -05:00
lib Add LFSR 2023-01-09 21:01:27 -05:00
rtl Silence warnings when converting memories to registers 2023-02-18 22:48:36 -05:00
tb Add LED blinker 2023-02-18 22:48:36 -05:00
.gitignore Add some more files to gitignore 2022-11-05 12:52:57 -04:00
.gitmodules Add LFSR 2023-01-09 21:01:27 -05:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
CONTRIBUTING Add licenses 2022-11-05 12:50:12 -04:00
COPYING Add licenses 2022-11-05 12:50:12 -04:00
Makefile Makefile: Fix synthesis dependencies 2023-02-18 22:48:36 -05:00