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ethernet
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WIP 100BASE-TX PHY
49 Commits 2 Branches 0 Tags 290 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
SystemVerilog 0.8%
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Sean Anderson ead545e85e Rename pmd to pmd_io 
This better reflects the function of the module (interfacing the
transciever via the I/O pins), and fits better with the naming scheme
used for other I/O modules.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-08-28 17:25:24 -04:00
rtl Rename pmd to pmd_io 2022-08-28 17:25:24 -04:00
tb Rename pmd to pmd_io 2022-08-28 17:25:24 -04:00
.gitignore Ignore post-synthesis verilog 2022-08-21 12:36:36 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Rename pmd to pmd_io 2022-08-28 17:25:24 -04:00