e2544d702f
This generates the appropriate output for MII receive signals. Because we don't have a clock synchronous to the recieved data, we may occasionally have some cycles which are 32 ns or 48 ns long (instead of the nominal 40 ns). This distorts the duty cycle to 38% or 58%, respectively, which is within the specified 35% to 65%. This does change the frequency to either 31 MHz or 21 MHz, respectively, which *is* a violation of the spec. This could be avoided by introducing a FIFO to smooth out any variations in jitter, like what RMII does. The generation of rx_clk is a bit tricky. We can use a combinatorial signal for the posedge, since that is what the rest of the logic is referenced to, However, we need to register the negedge to prevent an early (or late) ce from modifying the duty cycle. Signed-off-by: Sean Anderson <seanga2@gmail.com> |
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| rtl | ||
| tb | ||
| .gitignore | ||
| 4b5b.gtkw | ||
| Makefile | ||