dd4183991d
This module implements the I/O portion of the MII management interface. The output is delayed by 2 clocks in order to ensure that the external level shifter has switched directions before we drive it. The latency increase (around 16 ns) is not consequential, since we have around 300 ns from the rising edge of MDC before MDIO has to be valid. On the other end, the timing requirements for MDIO driven by the STA are very lenient (for them); MDIO only has to be valid for 10 ns on either side of the rising edge of MDC. This effectively means we must sample MDIO synchronously to MDC (not easy with nextpnr), or oversample by 50x. Fortunately, we have a 125 MHz clock which the rest of the phty runs off of. However, this basically makes 10x oversampling with the MII clock impossible. Signed-off-by: Sean Anderson <seanga2@gmail.com> |
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| rtl | ||
| tb | ||
| .gitignore | ||
| 4b5b.gtkw | ||
| Makefile | ||