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WIP 100BASE-TX PHY
53 Commits 2 Branches 0 Tags 290 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
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Sean Anderson d9602b6f78 Add MII management functions 
This adds a module implementing the the MII management functions (the
MDIO regs). For the moment, we just implement the standard registers.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-08-31 12:36:11 -04:00
rtl Add MII management functions 2022-08-31 12:36:11 -04:00
tb Add MII management functions 2022-08-31 12:36:11 -04:00
.gitignore Ignore post-synthesis verilog 2022-08-21 12:36:36 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Add MII management functions 2022-08-31 12:36:11 -04:00