skywater
/
ethernet
mirror of https://github.com/Forty-Bot/ethernet.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
WIP 100BASE-TX PHY
33 Commits 2 Branches 0 Tags 290 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
SystemVerilog 0.8%
Go to file
Sean Anderson cbbdbeef1c pcs: Assert CRS after TX_EN sooner 
24.6.1 requires that CRS goes high fewer than 4 cycles after TX_EN goes
high. This means we need to assert tx when we enter then START_J state,
not when we actually transmit a /J/. This also has the upside of
simplifying the logic a bit.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-08-24 12:10:52 -04:00
rtl pcs: Assert CRS after TX_EN sooner 2022-08-24 12:10:52 -04:00
tb Make testbenches a module 2022-08-21 12:36:28 -04:00
.gitignore Ignore post-synthesis verilog 2022-08-21 12:36:36 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Use MODULE variable for tests 2022-08-24 12:10:07 -04:00