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WIP 100BASE-TX PHY
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Verilog 50.1%
Python 46.8%
Makefile 2.3%
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Sean Anderson 6af697b4eb Initial support for post-placement simulation 
This isn't really useful for most modules (since the placement info is
if they were the only thing instantiated), but it should be a good base.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-10-16 17:52:27 -04:00
rtl Initial support for post-placement simulation 2022-10-16 17:52:27 -04:00
tb mdio:io: Don't drive mdio as X in testbench 2022-10-16 17:37:38 -04:00
.gitignore Ignore post-synthesis verilog 2022-08-21 12:36:36 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Initial support for post-placement simulation 2022-10-16 17:52:27 -04:00