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ethernet
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WIP 100BASE-TX PHY
65 Commits 2 Branches 0 Tags 290 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
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Sean Anderson 5ac40dbea2 pcs: data_?x -> ?x_data 
Rename signals to be properly heirarchal.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-10-16 18:58:29 -04:00
rtl pcs: data_?x -> ?x_data 2022-10-16 18:58:29 -04:00
tb pcs: data_?x -> ?x_data 2022-10-16 18:58:29 -04:00
.gitignore Ignore post-synthesis verilog 2022-08-21 12:36:36 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Store synthesis logs 2022-10-16 18:00:02 -04:00