skywater
/
ethernet
mirror of https://github.com/Forty-Bot/ethernet.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
WIP 100BASE-TX PHY
60 Commits 2 Branches 0 Tags 290 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
SystemVerilog 0.8%
Go to file
Sean Anderson 548e5b5b51 Convert all reg assignments to initial 
As it turns out,

	reg foo = 0;

is not the same as

	reg foo; initial foo = 0;

but instead is equivalent to

	reg foo; always @(*) foo = 0;

This is rather silly. Convert all existing (lucky) examples to the
second form.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-10-16 17:48:43 -04:00
rtl Convert all reg assignments to initial 2022-10-16 17:48:43 -04:00
tb mdio:io: Don't drive mdio as X in testbench 2022-10-16 17:37:38 -04:00
.gitignore Ignore post-synthesis verilog 2022-08-21 12:36:36 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Rename *post* targets to *synth* 2022-09-04 17:14:45 -04:00