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ethernet
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WIP 100BASE-TX PHY
81 Commits 2 Branches 0 Tags 290 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
SystemVerilog 0.8%
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Sean Anderson 4b55a822ab Rename test targets 
The dependencies for the test target never got updated when some modules
were renamed. Fix this.

Fixes: 494ef2a ("pcs: Split into rx/tx")
Fixes: cf0aed4 ("pmd_io: Rename to pmd_dp83223_rx")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-11-05 12:37:18 -04:00
rtl pcs: Add false_carrier signal 2022-11-05 12:37:18 -04:00
tb nrzi_encode: Fix test name 2022-11-05 12:37:18 -04:00
.gitignore Ignore post-synthesis verilog 2022-08-21 12:36:36 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Rename test targets 2022-11-05 12:37:18 -04:00