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ethernet
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WIP 100BASE-TX PHY
54 Commits 2 Branches 0 Tags 290 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
SystemVerilog 0.8%
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Sean Anderson 42c1e93338 Rename *post* targets to *synth* 
The post here originally stood for post-synthesis. To add support for
post-placement simulation and reduce ambiguity, rename these targets to
*synth*.
 		2022-09-04 17:14:45 -04:00
rtl Add MII management functions 2022-08-31 12:36:11 -04:00
tb Add MII management functions 2022-08-31 12:36:11 -04:00
.gitignore Ignore post-synthesis verilog 2022-08-21 12:36:36 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Rename *post* targets to *synth* 2022-09-04 17:14:45 -04:00