40 lines
683 B
Verilog
40 lines
683 B
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only
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/*
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* Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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*/
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`include "common.vh"
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module nrzi_decode (
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input clk,
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input [1:0] nrzi,
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input [1:0] nrzi_valid,
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output reg [1:0] nrz,
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output reg [1:0] nrz_valid
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);
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reg [1:0] nrz_next;
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reg nrzi_last;
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reg nrzi_last_next;
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always @(*) begin
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nrz_next[0] = nrzi[1] ^ nrzi[0];
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nrz_next[1] = nrzi[1] ^ nrzi_last;
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nrzi_last_next = nrzi_last;
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if (nrzi_valid != 0)
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nrzi_last_next = nrzi[1];
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if (nrzi_valid & 2)
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nrzi_last_next = nrzi[0];
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end
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always @(posedge clk) begin
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nrzi_last <= nrzi_last_next;
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nrz_valid <= nrzi_valid;
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nrz <= nrz_next;
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end
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`DUMP(0)
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endmodule
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