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ethernet
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WIP 100BASE-TX PHY
36 Commits 2 Branches 0 Tags 290 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
SystemVerilog 0.8%
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Sean Anderson 15ae994ad6 tb: Fix incorrect valid in send_recovered_bits 
At the end of the bitstream, we might not have enough bits for valid=2.
If we don't change it to valid=1, instead of marking an X as valid.

Fixes: d351291 ("Initial commit")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-08-24 12:18:39 -04:00
rtl pcs: Assert CRS after TX_EN sooner 2022-08-24 12:10:52 -04:00
tb tb: Fix incorrect valid in send_recovered_bits 2022-08-24 12:18:39 -04:00
.gitignore Ignore post-synthesis verilog 2022-08-21 12:36:36 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Use MODULE variable for tests 2022-08-24 12:10:07 -04:00