114 lines
1.9 KiB
Verilog
114 lines
1.9 KiB
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only
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/*
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* Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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*/
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`include "common.vh"
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`include "io.vh"
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module mii_io_rx (
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/* On-chip */
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input clk,
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input ce,
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input valid,
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input err,
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input [3:0] data,
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/* Off-chip */
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output reg rx_clk,
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output reg rx_dv,
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output reg rx_er,
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output reg [3:0] rxd
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);
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reg rx_clk_p_next, rx_clk_n, rx_clk_n_next;
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reg [1:0] state = HIGH, state_next;
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parameter LOW = 2;
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parameter RISING = 1;
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parameter HIGH = 0;
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always @(*) begin
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rx_clk_p_next = 0;
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rx_clk_n_next = 0;
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if (ce) begin
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state_next = LOW;
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end else case (state)
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LOW: begin
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state_next = RISING;
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end
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RISING: begin
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state_next = HIGH;
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rx_clk_n_next = 1;
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end
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HIGH: begin
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state_next = HIGH;
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rx_clk_p_next = 1;
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rx_clk_n_next = 1;
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end
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endcase
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end
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always @(posedge clk) begin
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state <= state_next;
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rx_clk_n <= rx_clk_n_next;
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end
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`ifdef SYNTHESIS
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SB_IO #(
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.PIN_TYPE(`PIN_OUTPUT_ALWAYS | `PIN_OUTPUT_DDR)
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) rx_clk_pin (
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.PACKAGE_PIN(rx_clk),
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.OUTPUT_CLK(clk),
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.D_OUT_0(rx_clk_p_next),
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.D_OUT_1(rx_clk_n)
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);
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SB_IO #(
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.PIN_TYPE(`PIN_OUTPUT_ALWAYS | `PIN_OUTPUT_REGISTERED)
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) rx_dv_pin (
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.PACKAGE_PIN(rx_dv),
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.CLOCK_ENABLE(ce),
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.OUTPUT_CLK(clk),
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.D_OUT_0(valid)
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);
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SB_IO #(
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.PIN_TYPE(`PIN_OUTPUT_ALWAYS | `PIN_OUTPUT_REGISTERED)
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) rx_er_pin (
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.PACKAGE_PIN(rx_er),
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.CLOCK_ENABLE(ce),
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.OUTPUT_CLK(clk),
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.D_OUT_0(err)
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);
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genvar i;
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generate for (i = 0; i < 4; i = i + 1) begin
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SB_IO #(
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.PIN_TYPE(`PIN_OUTPUT_ALWAYS | `PIN_OUTPUT_REGISTERED)
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) rxd_pin (
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.PACKAGE_PIN(rxd[i]),
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.CLOCK_ENABLE(ce),
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.OUTPUT_CLK(clk),
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.D_OUT_0(data[i])
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);
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end
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endgenerate
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`else
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always @(posedge clk) begin
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rx_clk <= rx_clk_p_next;
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if (ce) begin
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rx_dv <= valid;
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rx_er <= err;
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rxd <= data;
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end
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end
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always @(negedge clk)
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rx_clk <= rx_clk_n;
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`endif
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`DUMP(0)
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endmodule
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