0c2989b13c
The actitecture is overall fairly similar to the receive interface, except that the directions are mostly different. The timing is a bit easier, since we control the ce signal. Data is sampled one clock before tx_clk goes high, which is the earliest that it is guarantee'd to be valid. We could get an extra half-clock by having tx_clk go high at the negedge of clk, but it's unnecessary at the moment. Signed-off-by: Sean Anderson <seanga2@gmail.com> |
||
|---|---|---|
| rtl | ||
| tb | ||
| .gitignore | ||
| 4b5b.gtkw | ||
| Makefile | ||