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WIP 100BASE-TX PHY
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Verilog 50.1%
Python 46.8%
Makefile 2.3%
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Sean Anderson 050ecaade6 pmd: Fix wrong type of assignment 
This process used the wrong type of assignment. Fix it.

Fixes: 1d65661 ("Add pmd")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-08-28 12:21:02 -04:00
rtl pmd: Fix wrong type of assignment 2022-08-28 12:21:02 -04:00
tb Add MDIO I/O module 2022-08-28 12:21:02 -04:00
.gitignore Ignore post-synthesis verilog 2022-08-21 12:36:36 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Add MDIO I/O module 2022-08-28 12:21:02 -04:00