137 lines
2.9 KiB
Verilog
137 lines
2.9 KiB
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only OR CERN-OHL-S-2.0
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/*
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* Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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*
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* PHY with internal (unexposed) MII and a wishbone management interface
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*/
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`include "common.vh"
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`include "io.vh"
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module phy_internal (
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input clk_125,
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input clk_250,
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/* DP83223 */
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input indicate_data,
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input signal_detect,
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output request_data,
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/* MII */
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input mii_tx_ce,
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input mii_tx_en,
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input mii_tx_er,
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input [3:0] mii_txd,
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output mii_rx_ce,
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output mii_rx_dv,
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output mii_rx_er,
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output [3:0] mii_rxd,
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output mii_col,
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output mii_crs,
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/* Wishbone management */
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output wb_ack, wb_err,
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input wb_cyc, wb_stb, wb_we,
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input [4:0] wb_addr,
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input [15:0] wb_data_write,
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output [15:0] wb_data_read,
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/* Control/status */
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output link_status,
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output receiving,
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output false_carrier,
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output symbol_error
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);
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parameter WISHBONE = 1;
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parameter ENABLE_COUNTERS = 1;
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parameter COUNTER_WIDTH = 15;
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parameter [23:0] OUI = 0;
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parameter [5:0] MODEL = 0;
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parameter [3:0] REVISION = 0;
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wire isolate, tx_data, signal_status, link_monitor_test, descrambler_test;
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wire loopback, coltest;
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wire [1:0] rx_data, rx_data_valid;
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phy_core phy_core (
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.clk(clk_125),
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.tx_data(tx_data),
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.rx_data(rx_data),
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.rx_data_valid(rx_data_valid),
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.signal_status(signal_status),
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.tx_ce(mii_tx_ce),
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.tx_en(mii_tx_en),
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.txd(mii_txd),
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.tx_er(mii_tx_er),
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.rx_ce(mii_rx_ce),
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.rx_dv(mii_rx_dv),
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.rxd(mii_rxd),
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.rx_er(mii_rx_er),
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.crs(mii_crs),
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.col(mii_col),
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.loopback(loopback),
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.coltest(coltest),
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.link_monitor_test_mode(link_monitor_test),
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.descrambler_test_mode(descrambler_test),
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.link_status(link_status),
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.receiving(receiving),
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.false_carrier(false_carrier),
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.symbol_error(symbol_error)
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);
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pmd_dp83223 pmd (
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.clk_125(clk_125),
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.clk_250(clk_250),
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.signal_detect(signal_detect),
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.request_data(request_data),
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.indicate_data(indicate_data),
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.tx_data(tx_data),
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.rx_data(rx_data),
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.rx_data_valid(rx_data_valid),
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.signal_status(signal_status),
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.loopback(loopback)
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);
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generate if (WISHBONE) begin
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mdio_regs #(
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.OUI(OUI),
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.MODEL(MODEL),
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.REVISION(REVISION),
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.EMULATE_PULLUP(1'b1),
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.ENABLE_COUNTERS(ENABLE_COUNTERS),
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.COUNTER_WIDTH(COUNTER_WIDTH)
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) mdio_regs (
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.clk(clk_125),
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.ack(wb_ack),
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.err(wb_err),
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.cyc(wb_cyc),
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.stb(wb_stb),
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.we(wb_we),
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.addr(wb_addr),
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.data_write(wb_data_write),
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.data_read(wb_data_read),
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.link_status(link_status),
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.negative_wraparound(!rx_data_valid),
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.positive_wraparound(rx_data_valid[1]),
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.false_carrier(false_carrier),
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.symbol_error(symbol_error),
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.loopback(loopback),
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.isolate(isolate),
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.coltest(coltest),
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.descrambler_test(descrambler_test),
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.link_monitor_test(link_monitor_test)
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);
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end else begin
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assign wb_ack = 0;
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assign wb_err = wb_cyc && wb_stb;
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assign loopback = 0;
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assign coltest = 0;
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assign descrambler_test = 0;
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assign link_monitor_test = 0;
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end endgenerate
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endmodule
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