Commit Graph

12 Commits

Author SHA1 Message Date
Sean Anderson bc78d56f05 tb: util: Use RisingEdge for ClockEnable
Signals modified by cocotb tasks may not be visible to other tasks on
the same clock cycle. This was causing issues for recv_packet, because
it might not see the same values for ready/valid driven by ClockEnable
that the DUT sees. This was worked around by sampling on the RisingEdge.
However, this can cause recv_packet to miss data. Fix this by using
RisingEdge for ClockEnable, so everything can be sampled on the
FallingEdge.

Fixes: 52325f2 ("Add AXI stream replay buffer")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-03-01 19:19:31 -05:00
Sean Anderson 7c9ac42988 Add wishbone mux
This adds a simple wishbone mux. The idea is that each slave gets its
own address bit. This lends itself to extemely simple address decoding,
but uses up address space quickly. In theory, we could also give larger
addres space to some slaves, but currently lower bits have priority. The
testbench is also very simple. Since everything is combinatorial, we can
determine the outputs from the inputs exactly.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-02-18 22:48:36 -05:00
Sean Anderson afbb64023e tb: Move BIT to util
This function may be useful for other testbenches.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-02-18 22:48:36 -05:00
Sean Anderson 52325f241b Add AXI stream replay buffer
This implements an AXI stream buffer which allows replaying of the first
portion of each packet. The intent is to simplify the implementation of
CSMA/CD. This requires keeping 56 bytes of data to "replay" (slot time
minus the preamble). After these bytes are transmitted, we can only get
late collisions.

We always read from the buffer, as this simplifies the implementation
compared to some kind of hybrid fifo/skid buffer approach. The primary
design problem faced is in determining when it's OK to overwrite the
first byte in the packet. A naïve approach might be to allow overwriting
whenever the slave reads the last byte. However, in the case of a
54-byte packet, we will still need to allow replaying at this point (in
case there is a collision on the last byte). We can't just wait for
m_axis_ready to go high, because that would violate the AXI stream
protocol. To solve this, the slave must assert the done signal when it
is finished with the packet.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-11-30 18:14:23 -05:00
Sean Anderson f6f3f024e4 Add phy_core
This module integrates the PCS with the descrambler, implements the PMA
(which is just the link monitor), and implements loopback and coltest
functions. This is more of the PCS/PMA, but the descrambler is
technically part of the PMD, so it's the "core" instead.

We deviate from the standard in one important way: the link doesn't come
up until the descambler is locked. I think this makes sense, since if
the descrambler isn't locked, then the incoming data will be gibberish.
I suspect this isn't part of the standard because the descrambler
doesn't have a locked output in X3.263, so IEEE would have had to
specify it.

Loopback is actually implemented in the PMD, but it modifies the
behavior in several places. It disables collisions (unless
coltest is enabled). Additionally, we need to force the link up (to
avoid the lengthy stabilization timer), but ensure it is down for at
least once cycle (to ensure the descrambler desynchronizes).

On the test side, we just go through the "happy path," as many of the
edge conditions are tested for in the submodule tests. Several of those
tests are modified so that their helper functions can be reused in this
test. In particular, the rx path is now async so that we can feed it
rx_data.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-11-05 12:37:18 -04:00
Sean Anderson 4646500973 tb: Refactor out ClockEnable
Several interfaces have ce signals. Create a common function for driving
these signals, similar to the Clock function.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-27 13:09:30 -04:00
Sean Anderson 592ba14091 tb: Refactor out with_valids
Parametrizing a test over different methods of generating valid data
will be useful for other tests as well. Refactor it out. We have to bind
valids early in with_valids.test, otherwise we will end up binding
with_valids.valid by reference (causing all tests to use saw_valid).

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-24 12:25:07 -04:00
Sean Anderson 15ae994ad6 tb: Fix incorrect valid in send_recovered_bits
At the end of the bitstream, we might not have enough bits for valid=2.
If we don't change it to valid=1, instead of marking an X as valid.

Fixes: d351291 ("Initial commit")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-24 12:18:39 -04:00
Sean Anderson 6800b85a85 tb: Move print_list_at/compare_lists to util
These functions will be useful for other tests. Refactor them out into
utility functions.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-24 12:16:43 -04:00
Sean Anderson c1301ca31a tb: Break out the core of pcs_send_codes into its own function
The PMA also has to deal with "recoverd bitstreams" (that is, inputs which
can have 0, 1, or 2 valid bits). Export the core of pcs_send_codes into its
own function, as it is useful for generating these signals.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-08 00:23:55 -04:00
Sean Anderson 0c5f7fa905 tb: Parametrize rx tests
In the recieve tests, the harness often has a choice of how fast to feed
data to the module. Up to this point, we have always used the same
strategy (typically random), even when multiple strategies were used
when writing the test. Add parametrization to test different strategies
in each test run. The timing decorator is taken from the cocotb source,
since we can't pass parameters to cocotb.test directly any more.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2022-08-06 21:47:21 -04:00
Sean Anderson d351291ff8 Initial commit 2022-05-23 20:57:03 -04:00