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hub/phy_core: Export some status signals 

Export some status signals which can be used for LEDs. Hopefully this
will deliver an authentic blinkenlights experience.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
This commit is contained in:
Sean Anderson 2023-02-20 18:37:06 -05:00
parent b351beb9a0
commit f82fd2cac3
2 changed files with 19 additions and 8 deletions
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7
rtl/hub_core.v
View File

@ -4,7 +4,6 @@
*/ */
`include "common.vh" `include "common.vh"
`include "io.vh"
module hub_core ( module hub_core (
input clk, input clk,
@ -16,7 +15,10 @@ module hub_core (
output reg [PORT_COUNT - 1:0] tx_en, output reg [PORT_COUNT - 1:0] tx_en,
output reg [PORT_COUNT - 1:0] tx_er, output reg [PORT_COUNT - 1:0] tx_er,
output reg [PORT_COUNT * 4 - 1:0] txd output reg [PORT_COUNT * 4 - 1:0] txd,
/* Status; combinatorial! */
output reg jam, activity
); );
parameter PORT_COUNT = 4; parameter PORT_COUNT = 4;
@ -25,7 +27,6 @@ module hub_core (
localparam DATA_JAM = 4'h5; localparam DATA_JAM = 4'h5;
integer i; integer i;
reg jam, activity;
reg [PORT_BITS - 1:0] active_port; reg [PORT_BITS - 1:0] active_port;
reg [PORT_COUNT - 1:0] tx_en_next, tx_er_next; reg [PORT_COUNT - 1:0] tx_en_next, tx_er_next;
(* mem2reg *) (* mem2reg *)

20
rtl/phy_core.v
View File

@ -30,13 +30,16 @@ module phy_core (
output reg crs, output reg crs,
output reg col, output reg col,
/* Control */ /* Control/status */
input loopback, input loopback,
input coltest, input coltest,
input link_monitor_test_mode, input link_monitor_test_mode,
input descrambler_test_mode, input descrambler_test_mode,
output locked, output locked,
output reg link_status output reg link_status,
output receiving,
output reg false_carrier,
output reg symbol_error
); );
wire tx_bits, transmitting; wire tx_bits, transmitting;
@ -135,8 +138,6 @@ module phy_core (
link_status <= link_status_next; link_status <= link_status_next;
end end
wire receiving;
pcs_rx pcs_rx ( pcs_rx pcs_rx (
.clk(clk), .clk(clk),
.ce(rx_ce), .ce(rx_ce),
@ -150,7 +151,7 @@ module phy_core (
); );
/* /*
* NB: These signals are not required to be in any particular clock * NB: CRS and COL are not required to be in any particular clock
* domain (not that it matters). * domain (not that it matters).
*/ */
always @(*) begin always @(*) begin
@ -160,6 +161,15 @@ module phy_core (
col = transmitting; col = transmitting;
else if (loopback) else if (loopback)
col = 0; col = 0;
false_carrier = 0;
symbol_error = 0;
if (rx_ce && rx_er) begin
if (rx_dv)
symbol_error = 1;
else
false_carrier = 1;
end
end end
endmodule endmodule