diff --git a/rtl/hub_core.v b/rtl/hub_core.v
index e4852de..e751186 100644
--- a/rtl/hub_core.v
+++ b/rtl/hub_core.v
@@ -4,7 +4,6 @@
  */
 
 `include "common.vh"
-`include "io.vh"
 
 module hub_core (
 	input clk,
@@ -16,7 +15,10 @@ module hub_core (
 
 	output reg [PORT_COUNT - 1:0] tx_en,
 	output reg [PORT_COUNT - 1:0] tx_er,
-	output reg [PORT_COUNT * 4 - 1:0] txd
+	output reg [PORT_COUNT * 4 - 1:0] txd,
+
+	/* Status; combinatorial! */
+	output reg jam, activity
 );
 
 	parameter PORT_COUNT	= 4;
@@ -25,7 +27,6 @@ module hub_core (
 	localparam DATA_JAM	= 4'h5;
 
 	integer i;
-	reg jam, activity;
 	reg [PORT_BITS - 1:0] active_port;
 	reg [PORT_COUNT - 1:0] tx_en_next, tx_er_next;
 	(* mem2reg *)
diff --git a/rtl/phy_core.v b/rtl/phy_core.v
index 77c2642..25a8c5c 100644
--- a/rtl/phy_core.v
+++ b/rtl/phy_core.v
@@ -30,13 +30,16 @@ module phy_core (
 	output reg crs,
 	output reg col,
 
-	/* Control */
+	/* Control/status */
 	input loopback,
 	input coltest,
 	input link_monitor_test_mode,
 	input descrambler_test_mode,
 	output locked,
-	output reg link_status
+	output reg link_status,
+	output receiving,
+	output reg false_carrier,
+	output reg symbol_error
 );
 
 	wire tx_bits, transmitting;
@@ -135,8 +138,6 @@ module phy_core (
 		link_status <= link_status_next;
 	end
 
-	wire receiving;
-
 	pcs_rx pcs_rx (
 		.clk(clk),
 		.ce(rx_ce),
@@ -150,7 +151,7 @@ module phy_core (
 	);
 
 	/*
-	 * NB: These signals are not required to be in any particular clock
+	 * NB: CRS and COL are not required to be in any particular clock
 	 * domain (not that it matters).
 	 */
 	always @(*) begin
@@ -160,6 +161,15 @@ module phy_core (
 			col = transmitting;
 		else if (loopback)
 			col = 0;
+
+		false_carrier = 0;
+		symbol_error = 0;
+		if (rx_ce && rx_er) begin
+			if (rx_dv)
+				symbol_error = 1;
+			else
+				false_carrier = 1;
+		end
 	end
 
 endmodule