pmd: Delay signal_status/detect until data is valid
The data yielded by the PMD is not really valid until it has made its way through the pipeline. Delay it until the data is valid. As a side effect, this should also eliminate any metastability. This is not necessary for real hardware, but it allows us to to post-synthesis simulation (where we can't reach in and probe the internal valid signal). Additionally, ensure that the state is known by resetting it when we don't have a signal. Signed-off-by: Sean Anderson <seanga2@gmail.com>
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rtl/pmd.v
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rtl/pmd.v
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@ -23,13 +23,14 @@ module pmd (
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input rx,
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/* PMD */
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output reg signal_status,
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output signal_status,
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input pmd_data_tx,
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output reg [1:0] pmd_data_rx,
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output reg [1:0] pmd_data_rx_valid
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);
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reg [1:0] rx_p, rx_n;
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reg [3:0] sd_delay;
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`ifdef SYNTHESIS
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SB_IO #(
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@ -38,7 +39,7 @@ module pmd (
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) signal_detect_pin (
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.PACKAGE_PIN(signal_detect),
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.INPUT_CLK(rx_clk_125),
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.D_IN_0(signal_status)
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.D_IN_0(sd_delay[0])
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);
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SB_IO #(
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@ -52,7 +53,7 @@ module pmd (
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);
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`else
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always @(posedge rx_clk_125)
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signal_status <= signal_detect;
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sd_delay[0] <= signal_detect;
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always @(posedge rx_clk_250)
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rx_p[0] <= rx;
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@ -61,6 +62,17 @@ module pmd (
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rx_n[0] <= rx;
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`endif
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/*
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* Delay signal status until the known good data has had a chance to
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* make it through the pipeline. This isn't necessary for real hardware
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* (since signal status is asserted long after we have good data), but
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* it helps out during simulation. It also helps avoid metastability.
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*/
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always @(posedge rx_clk_125)
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sd_delay[3:1] <= sd_delay[2:0];
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assign signal_status = sd_delay[3];
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/*
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* Get things into the rx_clk_250 domain so that we sample posedge before
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* negedge. Without this we can have a negedge which happens before the
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@ -135,8 +147,10 @@ module pmd (
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else
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valid_next = valid;
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if (!signal_status)
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if (!signal_status) begin
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state_next = A;
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valid_next = 0;
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end
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pmd_data_rx_next[0] = rx_d[2];
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pmd_data_rx_valid_next = 1;
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