skywater
/
ethernet
mirror of https://github.com/Forty-Bot/ethernet.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
WIP 100BASE-TX PHY
13 Commits 2 Branches 0 Tags 285 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
SystemVerilog 0.8%
Go to file
Sean Anderson d8ce1652ae pmd: Delay signal_status/detect until data is valid 
The data yielded by the PMD is not really valid until it has made its
way through the pipeline. Delay it until the data is valid. As a side
effect, this should also eliminate any metastability. This is not
necessary for real hardware, but it allows us to to post-synthesis
simulation (where we can't reach in and probe the internal valid
signal).

Additionally, ensure that the state is known by resetting it when we
don't have a signal.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-08-06 21:47:21 -04:00
rtl pmd: Delay signal_status/detect until data is valid 2022-08-06 21:47:21 -04:00
tb tb: pcs: Send packet spacing packets immediately 2022-08-06 21:47:21 -04:00
.gitignore Initial commit 2022-05-23 20:57:03 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Initial commit 2022-05-23 20:57:03 -04:00