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pmd_dp83223_rx: Don't use SB_IO for signal_detect 

The flip-flops internal to the SB_IO can't have initial values and
can't be reset. So before the first clock the data out will be X. This
results in a simulation-synthesis mismatch, as sd_delay will be wrong
for one clock cycle. Fix this by removing the SB_IO cell, as the timing
of this signal isn't critical.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
This commit is contained in:
Sean Anderson 2023-02-20 18:21:44 -05:00
parent 83d805bb79
commit cc29d2050c
1 changed files with 2 additions and 14 deletions
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16
rtl/pmd_dp83223_rx.v
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@ -28,17 +28,9 @@ module pmd_dp83223_rx (
reg [1:0] rx_p, rx_n; reg [1:0] rx_p, rx_n;
reg [4:0] sd_delay; reg [4:0] sd_delay;
initial sd_delay[4:1] = 4'b0; initial sd_delay[4:0] = 5'b0;
`ifdef SYNTHESIS `ifdef SYNTHESIS
SB_IO #(
.PIN_TYPE(`PIN_OUTPUT_NEVER | `PIN_INPUT_REGISTERED),
) signal_detect_pin (
.PACKAGE_PIN(signal_detect),
.INPUT_CLK(clk_125),
.D_IN_0(sd_delay[0])
);
SB_IO #( SB_IO #(
.PIN_TYPE(`PIN_OUTPUT_NEVER | `PIN_INPUT_DDR), .PIN_TYPE(`PIN_OUTPUT_NEVER | `PIN_INPUT_DDR),
) rx_data_pin ( ) rx_data_pin (
@ -48,10 +40,6 @@ module pmd_dp83223_rx (
.D_IN_1(rx_n[0]) .D_IN_1(rx_n[0])
); );
`else `else
initial sd_delay[0] = 0;
always @(posedge clk_125)
sd_delay[0] <= signal_detect;
always @(posedge clk_250) always @(posedge clk_250)
rx_p[0] <= indicate_data; rx_p[0] <= indicate_data;
@ -66,7 +54,7 @@ module pmd_dp83223_rx (
* it helps out during simulation. It also helps avoid metastability. * it helps out during simulation. It also helps avoid metastability.
*/ */
always @(posedge clk_125) always @(posedge clk_125)
sd_delay[4:1] <= sd_delay[3:0]; sd_delay[4:0] <= { sd_delay[3:0], signal_detect };
assign signal_status = sd_delay[4]; assign signal_status = sd_delay[4];