From cc29d2050c445d679c4c19c2583c3fff08f062ce Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Mon, 20 Feb 2023 18:21:44 -0500 Subject: [PATCH] pmd_dp83223_rx: Don't use SB_IO for signal_detect The flip-flops internal to the SB_IO can't have initial values and can't be reset. So before the first clock the data out will be X. This results in a simulation-synthesis mismatch, as sd_delay will be wrong for one clock cycle. Fix this by removing the SB_IO cell, as the timing of this signal isn't critical. Signed-off-by: Sean Anderson --- rtl/pmd_dp83223_rx.v | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/rtl/pmd_dp83223_rx.v b/rtl/pmd_dp83223_rx.v index 7a73d3c..1669b44 100644 --- a/rtl/pmd_dp83223_rx.v +++ b/rtl/pmd_dp83223_rx.v @@ -28,17 +28,9 @@ module pmd_dp83223_rx ( reg [1:0] rx_p, rx_n; reg [4:0] sd_delay; - initial sd_delay[4:1] = 4'b0; + initial sd_delay[4:0] = 5'b0; `ifdef SYNTHESIS - SB_IO #( - .PIN_TYPE(`PIN_OUTPUT_NEVER | `PIN_INPUT_REGISTERED), - ) signal_detect_pin ( - .PACKAGE_PIN(signal_detect), - .INPUT_CLK(clk_125), - .D_IN_0(sd_delay[0]) - ); - SB_IO #( .PIN_TYPE(`PIN_OUTPUT_NEVER | `PIN_INPUT_DDR), ) rx_data_pin ( @@ -48,10 +40,6 @@ module pmd_dp83223_rx ( .D_IN_1(rx_n[0]) ); `else - initial sd_delay[0] = 0; - always @(posedge clk_125) - sd_delay[0] <= signal_detect; - always @(posedge clk_250) rx_p[0] <= indicate_data; @@ -66,7 +54,7 @@ module pmd_dp83223_rx ( * it helps out during simulation. It also helps avoid metastability. */ always @(posedge clk_125) - sd_delay[4:1] <= sd_delay[3:0]; + sd_delay[4:0] <= { sd_delay[3:0], signal_detect }; assign signal_status = sd_delay[4];