Convert all reg assignments to initial
As it turns out, reg foo = 0; is not the same as reg foo; initial foo = 0; but instead is equivalent to reg foo; always @(*) foo = 0; This is rather silly. Convert all existing (lucky) examples to the second form. Signed-off-by: Sean Anderson <seanga2@gmail.com>
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@ -30,7 +30,8 @@ module descramble (
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* required in certain situations.
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* required in certain situations.
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*/
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*/
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localparam CONSECUTIVE_IDLES = 5'd29;
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localparam CONSECUTIVE_IDLES = 5'd29;
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reg [4:0] idle_counter = CONSECUTIVE_IDLES, idle_counter_next;
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reg [4:0] idle_counter, idle_counter_next;
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initial idle_counter = CONSECUTIVE_IDLES;
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/*
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/*
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* The amount of time without recieving consecutive idles before we
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* The amount of time without recieving consecutive idles before we
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@ -48,8 +48,9 @@ module mdio (
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reg [15:0] data_next;
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reg [15:0] data_next;
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reg bad, bad_next, saved_err, saved_err_next;
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reg bad, bad_next, saved_err, saved_err_next;
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reg [2:0] state = IDLE, state_next;
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reg [2:0] state, state_next;
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reg [4:0] state_counter, state_counter_next;
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reg [4:0] state_counter, state_counter_next;
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initial state = IDLE;
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/*
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/*
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* NB: stb_next and data_next are assigned to stb and data_write every
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* NB: stb_next and data_next are assigned to stb and data_write every
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@ -23,7 +23,8 @@ module mdio_io (
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reg mdi_next;
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reg mdi_next;
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reg [1:0] last_mdc;
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reg [1:0] last_mdc;
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/* Two clock delay to allow the level shifter to reverse direction */
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/* Two clock delay to allow the level shifter to reverse direction */
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reg [2:0] oe = 0;
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reg [2:0] oe;
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initial oe = 0;
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`ifdef SYNTHESIS
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`ifdef SYNTHESIS
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SB_IO #(
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SB_IO #(
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@ -26,7 +26,6 @@ module mii_io_tx (
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reg ce_next, raw_enable;
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reg ce_next, raw_enable;
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reg tx_clk_p_next, tx_clk_n, tx_clk_n_next;
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reg tx_clk_p_next, tx_clk_n, tx_clk_n_next;
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reg [2:0] counter, counter_next;
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reg [2:0] counter, counter_next;
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/* I have no idea why we need to use initial... */
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initial counter = 4;
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initial counter = 4;
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always @(*) begin
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always @(*) begin
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@ -112,8 +112,10 @@ module pmd_io (
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localparam C = 2;
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localparam C = 2;
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localparam D = 3;
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localparam D = 3;
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reg [1:0] state = A, state_next;
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reg [1:0] state, state_next;
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reg valid = 0, valid_next;
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initial state = A;
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reg valid, valid_next;
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initial valid = 0;
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reg [1:0] pmd_data_rx_next, pmd_data_rx_valid_next;
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reg [1:0] pmd_data_rx_next, pmd_data_rx_valid_next;
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reg [3:0] rx_r, rx_f;
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reg [3:0] rx_r, rx_f;
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@ -12,7 +12,8 @@ module scramble (
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);
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);
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reg lfsr_next;
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reg lfsr_next;
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reg [10:0] lfsr = 10'h3ff;
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reg [10:0] lfsr;
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initial lfsr = 10'h3ff;
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always @(*) begin
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always @(*) begin
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lfsr_next = lfsr[8] ^ lfsr[10];
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lfsr_next = lfsr[8] ^ lfsr[10];
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