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tb: Refactor out ClockEnable 

Several interfaces have ce signals. Create a common function for driving
these signals, similar to the Clock function.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
This commit is contained in:
Sean Anderson 2022-08-27 13:09:30 -04:00
parent 12a4678442
commit 4646500973
2 changed files with 12 additions and 11 deletions
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13
tb/pcs.py
View File

@ -10,7 +10,8 @@ from cocotb.regression import TestFactory
from cocotb.triggers import ClockCycles, Edge, RisingEdge, FallingEdge, Timer
from cocotb.types import LogicArray
from .util import alist, classproperty, ReverseList, send_recovered_bits, timeout, with_valids
from .util import alist, ClockEnable, classproperty, ReverseList, send_recovered_bits, \
timeout, with_valids
class Code(enum.Enum):
_0 = (0b11110, '0')
@ -200,19 +201,11 @@ async def pcs_send_codes(pcs, codes, valids):
@cocotb.test(timeout_time=10, timeout_unit='us')
async def test_tx(pcs):
async def tx_ce():
pcs.tx_ce.value = 1
while True:
await ClockCycles(pcs.tx_clk, 1, False)
pcs.tx_ce.value = 0
await ClockCycles(pcs.tx_clk, 4, False)
pcs.tx_ce.value = 1
pcs.tx_en.value = 0
pcs.tx_er.value = 0
pcs.txd.value = LogicArray("XXXX")
pcs.link_status.value = 1
await cocotb.start(tx_ce())
await cocotb.start(ClockEnable(pcs.tx_clk, pcs.tx_ce, 5))
await Timer(1)
await cocotb.start(Clock(pcs.tx_clk, 8, units='ns').start())
await FallingEdge(pcs.tx_ce)

10
tb/util.py
View File

@ -6,7 +6,7 @@ import random
import cocotb
from cocotb.result import SimTimeoutError
from cocotb.triggers import with_timeout, FallingEdge
from cocotb.triggers import ClockCycles, FallingEdge, with_timeout
from cocotb.types import LogicArray
async def alist(xs):
@ -133,3 +133,11 @@ def compare_lists(ins, outs):
print_list_at(ins, idx)
print_list_at(outs, idx)
assert False, "Differring bit"
async def ClockEnable(clk, ce, ratio):
ce.value = 1
while True:
await ClockCycles(clk, 1, False)
ce.value = 0
await ClockCycles(clk, ratio - 1, False)
ce.value = 1