tb: Refactor out ClockEnable
Several interfaces have ce signals. Create a common function for driving these signals, similar to the Clock function. Signed-off-by: Sean Anderson <seanga2@gmail.com>
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13
tb/pcs.py
13
tb/pcs.py
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@ -10,7 +10,8 @@ from cocotb.regression import TestFactory
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from cocotb.triggers import ClockCycles, Edge, RisingEdge, FallingEdge, Timer
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from cocotb.triggers import ClockCycles, Edge, RisingEdge, FallingEdge, Timer
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from cocotb.types import LogicArray
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from cocotb.types import LogicArray
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from .util import alist, classproperty, ReverseList, send_recovered_bits, timeout, with_valids
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from .util import alist, ClockEnable, classproperty, ReverseList, send_recovered_bits, \
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timeout, with_valids
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class Code(enum.Enum):
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class Code(enum.Enum):
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_0 = (0b11110, '0')
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_0 = (0b11110, '0')
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@ -200,19 +201,11 @@ async def pcs_send_codes(pcs, codes, valids):
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@cocotb.test(timeout_time=10, timeout_unit='us')
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@cocotb.test(timeout_time=10, timeout_unit='us')
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async def test_tx(pcs):
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async def test_tx(pcs):
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async def tx_ce():
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pcs.tx_ce.value = 1
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while True:
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await ClockCycles(pcs.tx_clk, 1, False)
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pcs.tx_ce.value = 0
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await ClockCycles(pcs.tx_clk, 4, False)
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pcs.tx_ce.value = 1
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pcs.tx_en.value = 0
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pcs.tx_en.value = 0
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pcs.tx_er.value = 0
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pcs.tx_er.value = 0
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pcs.txd.value = LogicArray("XXXX")
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pcs.txd.value = LogicArray("XXXX")
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pcs.link_status.value = 1
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pcs.link_status.value = 1
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await cocotb.start(tx_ce())
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await cocotb.start(ClockEnable(pcs.tx_clk, pcs.tx_ce, 5))
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await Timer(1)
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await Timer(1)
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await cocotb.start(Clock(pcs.tx_clk, 8, units='ns').start())
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await cocotb.start(Clock(pcs.tx_clk, 8, units='ns').start())
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await FallingEdge(pcs.tx_ce)
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await FallingEdge(pcs.tx_ce)
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10
tb/util.py
10
tb/util.py
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@ -6,7 +6,7 @@ import random
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import cocotb
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import cocotb
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from cocotb.result import SimTimeoutError
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from cocotb.result import SimTimeoutError
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from cocotb.triggers import with_timeout, FallingEdge
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from cocotb.triggers import ClockCycles, FallingEdge, with_timeout
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from cocotb.types import LogicArray
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from cocotb.types import LogicArray
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async def alist(xs):
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async def alist(xs):
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@ -133,3 +133,11 @@ def compare_lists(ins, outs):
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print_list_at(ins, idx)
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print_list_at(ins, idx)
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print_list_at(outs, idx)
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print_list_at(outs, idx)
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assert False, "Differring bit"
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assert False, "Differring bit"
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async def ClockEnable(clk, ce, ratio):
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ce.value = 1
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while True:
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await ClockCycles(clk, 1, False)
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ce.value = 0
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await ClockCycles(clk, ratio - 1, False)
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ce.value = 1
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