162 lines
2.8 KiB
Coq
162 lines
2.8 KiB
Coq
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// SPDX-License-Identifier: AGPL-3.0-Only
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/*
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* Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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*/
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`include "common.vh"
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`include "pcs.vh"
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`timescale 1ns/1ns
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/* Transmit process */
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module pcs_tx (
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/* MII */
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input clk,
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input ce,
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input enable,
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input [3:0] data,
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input err,
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/* PMA */
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output bits,
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input link_status,
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/* Internal */
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output reg tx
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);
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localparam IDLE = 0;
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localparam START_J = 1;
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localparam START_K = 2;
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localparam ERROR_J = 3;
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localparam ERROR_K = 4;
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localparam ERROR = 5;
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localparam DATA = 6;
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localparam END_T = 7;
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localparam END_R = 8;
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reg [3:0] last_data;
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reg tx_next;
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reg [4:0] code, code_next;
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reg [3:0] state, state_next;
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initial tx = 0;
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initial code = `CODE_I;
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initial state = IDLE;
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always @(*) begin
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case (last_data)
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4'h0: code_next = `CODE_0;
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4'h1: code_next = `CODE_1;
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4'h2: code_next = `CODE_2;
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4'h3: code_next = `CODE_3;
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4'h4: code_next = `CODE_4;
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4'h5: code_next = `CODE_5;
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4'h6: code_next = `CODE_6;
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4'h7: code_next = `CODE_7;
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4'h8: code_next = `CODE_8;
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4'h9: code_next = `CODE_9;
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4'hA: code_next = `CODE_A;
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4'hB: code_next = `CODE_B;
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4'hC: code_next = `CODE_C;
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4'hD: code_next = `CODE_D;
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4'hE: code_next = `CODE_E;
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4'hF: code_next = `CODE_F;
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endcase
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tx_next = tx;
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if (enable) begin
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if (err)
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state_next = ERROR;
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else
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state_next = DATA;
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end else begin
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state_next = END_T;
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end
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case (state)
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IDLE: begin
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tx_next = 0;
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code_next = `CODE_I;
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state_next = IDLE;
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if (enable) begin
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tx_next = 1;
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if (err)
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state_next = ERROR_J;
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else
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state_next = START_J;
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end
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end
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START_J: begin
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code_next = `CODE_J;
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if (err)
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state_next = ERROR_K;
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else
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state_next = START_K;
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end
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START_K: begin
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code_next = `CODE_K;
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end
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ERROR_J: begin
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code_next = `CODE_J;
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state_next = ERROR_K;
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end
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ERROR_K: begin
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code_next = `CODE_K;
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state_next = ERROR;
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end
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ERROR: begin
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code_next = `CODE_H;
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end
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DATA: ;
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END_T: begin
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tx_next = 0;
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code_next = `CODE_T;
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state_next = END_R;
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end
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END_R: begin
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code_next = `CODE_R;
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state_next = IDLE;
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end
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endcase
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if (!link_status) begin
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tx_next = 0;
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code_next = `CODE_I;
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state_next = IDLE;
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end
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end
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always @(posedge clk) begin
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if (ce) begin
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last_data <= data;
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tx <= tx_next;
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code <= code_next;
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state <= state_next;
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end else begin
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code <= code << 1;
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end
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end
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`ifndef SYNTHESIS
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reg [255:0] state_text;
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always @(*) begin
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case (state)
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IDLE: state_text = "IDLE";
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START_J: state_text = "START_J";
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START_K: state_text = "START_K";
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ERROR_J: state_text = "ERROR_J";
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ERROR_K: state_text = "ERROR_K";
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ERROR: state_text = "ERROR";
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DATA: state_text = "DATA";
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END_T: state_text = "END_T";
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END_R: state_text = "END_R";
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endcase
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end
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`endif
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/* Transmit bits process */
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assign bits = code[4];
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endmodule
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