riscv

riscv synced commits to mwk/emulate-priority at riscv/yosys from mirror 2021-05-25 00:56:28 -05:00

riscv synced new reference mwk/emulate-priority to riscv/yosys from mirror 2021-05-25 00:56:28 -05:00

riscv synced commits to mwk/mem-inference at riscv/yosys from mirror 2021-05-25 00:56:28 -05:00

cf41e0d904 Ensure memory offset/size is aligned to largest port width.

0be6fce244 memory_share: Improve sat-based port sharing.

6062fd6980 memory_share: Add -nosat, -nowide flags.

8697b796e5 memory_share: Recognize wide read ports.

f1cb53b5b9 memory_share: Improve same-address merging, recognize wide write ports.

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riscv synced commits to mwk/mem-inference at riscv/yosys from mirror 2021-05-24 16:56:28 -05:00

97d0c30b69 Ensure memory offset/size is aligned to largest port width.

5c6a95a90e memory_share: Improve sat-based port sharing.

d7fbcc0842 memory_share: Add -nosat, -nowide flags.

d0a36b8a93 memory_share: Recognize wide read ports.

657355090c memory_share: Improve same-address merging, recognize wide write ports.

Compare 38 commits »

riscv synced commits to mwk/mem-priority-mask at riscv/yosys from mirror 2021-05-24 16:56:28 -05:00

riscv synced new reference mwk/mem-priority-mask to riscv/yosys from mirror 2021-05-24 16:56:28 -05:00

riscv synced commits to master at riscv/yosys from mirror 2021-05-24 16:56:27 -05:00

835688bf80 opt_mem_feedback: Rewrite feedback path finding logic.

b706adb809 opt_mem_feedback: Convert to Mem helpers.

dbfd0b61e3 hashlib: Add a hash for bool.

5488c69d2a Add a .mailmap file.

c9dc7d5928 Merge pull request #2779 from YosysHQ/mwk/nuke-travis

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