riscv

riscv synced commits to lofty/abc9-output-conflict at riscv/yosys from mirror 2022-05-10 13:50:11 -05:00

riscv synced new reference lofty/abc9-output-conflict to riscv/yosys from mirror 2022-05-10 13:50:11 -05:00

riscv synced commits to master at riscv/OpenFPGA from mirror 2022-05-10 05:50:17 -05:00

1363de599e Merge pull request #649 from lnis-uofu/dependabot/submodules/yosys-plugins-00590be

df7ce3262c Bump yosys-plugins from `cfd794b` to `00590be`

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riscv synced commits to master at riscv/OpenFPGA from mirror 2022-05-09 21:40:16 -05:00

c794aa58dd Merge pull request #648 from lnis-uofu/patch_update

aba7289bb3 Updated Patch Count

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riscv synced and deleted reference micko/test_ci at riscv/yosys from mirror 2022-05-09 21:30:10 -05:00

riscv synced commits to master at riscv/yosys from mirror 2022-05-09 21:30:10 -05:00

c862b1dbfb Bump version

riscv synced and deleted reference negedge_ff at riscv/OpenFPGA from mirror 2022-05-09 13:30:17 -05:00

riscv synced commits to master at riscv/OpenFPGA from mirror 2022-05-09 13:30:17 -05:00

2b052388c8 Merge pull request #647 from lnis-uofu/negedge_ff

b4f9453c00 [ci] downgrade ubuntu version in runner due to renamed packages in scripts

0f56dbcb92 [ci] debug

52b348c6db [ci] debug

15617392ae [ci] debugging

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riscv synced commits to lofty/rename-scramble_name at riscv/yosys from mirror 2022-05-09 13:20:11 -05:00

6e7b666fd6 rename: add -scramble-name option to randomly rename selections

aaa6566088 rename: add -scramble-name option to randomly rename selections

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riscv synced commits to master at riscv/yosys from mirror 2022-05-09 13:20:11 -05:00

587e09d551 Merge pull request #3305 from jix/sva_value_change_logic

5ca2ee0c31 Merge pull request #3297 from jix/sva_nested_clk_else

a855d62b42 verific: Improve logic generated for SVA value change expressions

96f64f4788 verific: Fix conditions of SVAs with explicit clocks within procedures

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riscv synced commits to micko/test_ci at riscv/yosys from mirror 2022-05-09 13:20:11 -05:00

riscv synced new reference micko/test_ci to riscv/yosys from mirror 2022-05-09 13:20:11 -05:00

riscv synced commits to negedge_ff at riscv/OpenFPGA from mirror 2022-05-09 05:20:20 -05:00

riscv synced new reference negedge_ff to riscv/OpenFPGA from mirror 2022-05-09 05:20:20 -05:00

riscv synced and deleted reference open_pdks_264 at riscv/caravel from mirror 2022-05-09 05:20:17 -05:00

riscv synced commits to main at riscv/caravel from mirror 2022-05-09 05:20:17 -05:00

44a83f90eb add links to litex core (#96)

d882f42803 Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90)

a2ccbd9e7e Modified the set_user_id.py script so that mode "-report" returns a valid value. (#93)

80c7d29412 A minor correction the gen_gpio_defaults.py script to ensure that (#95)

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riscv synced and deleted reference another_gpio_defaults_script_fix at riscv/caravel from mirror 2022-05-09 05:20:16 -05:00

riscv synced and deleted reference fix_set_user_id_reportmode at riscv/caravel from mirror 2022-05-09 05:20:16 -05:00

riscv synced and deleted reference fix_simple_por at riscv/caravel from mirror 2022-05-09 05:20:16 -05:00

riscv synced and deleted reference mattvenn-patch-1 at riscv/caravel from mirror 2022-05-09 05:20:16 -05:00