mirror of https://github.com/YosysHQ/yosys.git
2abe38e73e
The previous code for rerouting wires when inserting tristate buffers was overcomplicated and didn't handle all cases correctly (in particular, only cell connections were rewired — internal connections were not). |
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| .. | ||
| .gitignore | ||
| aigmap.ys | ||
| autopurge.ys | ||
| clkbufmap.ys | ||
| dff2dffs.ys | ||
| extractinv.ys | ||
| iopadmap.ys | ||
| mem_simple_4x1_cells.v | ||
| mem_simple_4x1_map.v | ||
| mem_simple_4x1_runtest.sh | ||
| mem_simple_4x1_tb.v | ||
| mem_simple_4x1_uut.v | ||
| recursive.v | ||
| recursive_map.v | ||
| recursive_runtest.sh | ||
| run-test.sh | ||
| techmap_replace.ys | ||
| wireinit.ys | ||