mirror of https://github.com/YosysHQ/yosys.git
77 lines
2.0 KiB
Verilog
77 lines
2.0 KiB
Verilog
`default_nettype none
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module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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(input wire write_enable, clk,
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input wire [DATA_WIDTH-1:0] data_in,
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input wire [ADDRESS_WIDTH-1:0] address_in,
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output wire [DATA_WIDTH-1:0] data_out);
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localparam WORD = (DATA_WIDTH-1);
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localparam DEPTH = (2**ADDRESS_WIDTH-1);
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reg [WORD:0] data_out_r;
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reg [WORD:0] memory [0:DEPTH];
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always @(posedge clk) begin
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if (write_enable)
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memory[address_in] <= data_in;
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data_out_r <= memory[address_in];
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end
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assign data_out = data_out_r;
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endmodule // sync_ram_sp
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module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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(input wire clk, write_enable,
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input wire [DATA_WIDTH-1:0] data_in,
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input wire [ADDRESS_WIDTH-1:0] address_in_r, address_in_w,
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output wire [DATA_WIDTH-1:0] data_out);
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localparam WORD = (DATA_WIDTH-1);
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localparam DEPTH = (2**ADDRESS_WIDTH-1);
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reg [WORD:0] data_out_r;
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reg [WORD:0] memory [0:DEPTH];
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always @(posedge clk) begin
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if (write_enable)
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memory[address_in_w] <= data_in;
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data_out_r <= memory[address_in_r];
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end
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assign data_out = data_out_r;
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endmodule // sync_ram_sdp
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module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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(input wire clk_a, clk_b,
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input wire write_enable_a, write_enable_b,
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input wire read_enable_a, read_enable_b,
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input wire [DATA_WIDTH-1:0] write_data_a, write_data_b,
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input wire [ADDRESS_WIDTH-1:0] addr_a, addr_b,
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output reg [DATA_WIDTH-1:0] read_data_a, read_data_b);
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localparam WORD = (DATA_WIDTH-1);
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localparam DEPTH = (2**ADDRESS_WIDTH-1);
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reg [WORD:0] mem [0:DEPTH];
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always @(posedge clk_a) begin
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if (write_enable_a)
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mem[addr_a] <= write_data_a;
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else
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read_data_a <= mem[addr_a];
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end
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always @(posedge clk_b) begin
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if (write_enable_b)
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mem[addr_b] <= write_data_b;
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else
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read_data_b <= mem[addr_b];
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end
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endmodule // sync_ram_tdp
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