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13 lines
530 B
Plaintext
13 lines
530 B
Plaintext
read_verilog adffs.v
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proc
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#async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
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flatten
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equiv_opt -multiclock -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:EFX_GBUFCE
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select -assert-count 4 t:EFX_FF
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select -assert-count 2 t:EFX_LUT4
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select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D
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