Eddie Hung 810f8c5dbd Merge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanup		2019-07-02 09:21:02 -07:00
..
tests	Improved xilinx "bram1" test	2015-04-09 17:12:12 +02:00
.gitignore	Added support for initialized xilinx brams	2015-04-06 17:07:10 +02:00
Makefile.inc	install *_nowide.lut files	2019-06-29 19:37:04 -07:00
abc_xc7.box	Update comment on boxes	2019-06-26 20:00:15 -07:00
abc_xc7.lut	Simplify comment	2019-06-17 19:14:41 -07:00
abc_xc7_nowide.lut	Add _nowide variants of LUT libraries in -nowidelut flows	2019-06-26 10:23:29 -07:00
arith_map.v	Instead of MUXCY/XORCY use CARRY4 (with timing)	2019-05-21 16:19:45 -07:00
brams.txt	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
brams_bb.v	Remove WIP ABC9 flop support	2019-06-14 10:37:52 -07:00
brams_init.py	Squelch trailing whitespace, including meta-whitespace	2018-03-11 16:03:41 +01:00
brams_map.v	Revert BRAM WRITE_MODE changes.	2019-03-04 09:22:22 -08:00
cells_map.v	Cleanup SRL inference/make more consistent	2019-06-29 21:42:20 -07:00
cells_sim.v	Refactor for one "abc_carry" attribute on module	2019-06-27 16:07:14 -07:00
cells_xtra.sh	Merge remote-tracking branch 'origin/master' into xaig	2019-06-25 09:33:11 -07:00
cells_xtra.v	Merge remote-tracking branch 'origin/master' into xaig	2019-06-25 09:33:11 -07:00
drams.txt	Add RAM32X1D support	2019-06-24 16:16:50 -07:00
drams_map.v	Add RAM32X1D support	2019-06-24 16:16:50 -07:00
ff_map.v	Cleanup	2019-06-05 12:28:46 -07:00
lut_map.v	Really permute Xilinx LUT mappings as default LUT6.I5:A6	2019-06-18 11:48:48 -07:00
synth_xilinx.cc	Remove peepopt call in synth_xilinx since already in synth -run coarse	2019-06-28 12:53:38 -07:00