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riscv
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yosys
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https://github.com/YosysHQ/yosys.git
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f6e6e9b844
yosys
/
backends
History
Clifford Wolf
968ae31cac
Added support for dump -append
2014-02-04 23:45:30 +01:00
..
autotest
Fixed gentb_constant handling in autotest backend
2013-12-04 09:09:42 +01:00
blif
Added "top" attribute to mark top module in hierarchy
2013-11-24 05:03:43 +01:00
btor
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
2014-02-03 13:01:45 +01:00
edif
Replaced RTLIL::Const::str with generic decoder method
2013-12-04 14:14:05 +01:00
ilang
Added support for dump -append
2014-02-04 23:45:30 +01:00
intersynth
beautified write_intersynth
2014-01-25 20:16:38 +01:00
spice
Added "top" attribute to mark top module in hierarchy
2013-11-24 05:03:43 +01:00
verilog
Added support for non-const === and !== (for miter circuits)
2013-12-27 14:20:15 +01:00