mirror of https://github.com/YosysHQ/yosys.git
67 lines
3.7 KiB
Makefile
67 lines
3.7 KiB
Makefile
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OBJS += techlibs/xilinx/synth_xilinx.o
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GENFILES += techlibs/xilinx/brams_init_36.vh
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GENFILES += techlibs/xilinx/brams_init_32.vh
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GENFILES += techlibs/xilinx/brams_init_18.vh
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GENFILES += techlibs/xilinx/brams_init_16.vh
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GENFILES += techlibs/xilinx/brams_init_9.vh
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GENFILES += techlibs/xilinx/brams_init_8.vh
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EXTRA_OBJS += techlibs/xilinx/brams_init.mk
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.SECONDARY: techlibs/xilinx/brams_init.mk
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techlibs/xilinx/brams_init.mk: techlibs/xilinx/brams_init.py
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$(Q) mkdir -p techlibs/xilinx
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$(P) $(PYTHON_EXECUTABLE) $<
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$(Q) touch $@
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techlibs/xilinx/brams_init_36.vh: techlibs/xilinx/brams_init.mk
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techlibs/xilinx/brams_init_32.vh: techlibs/xilinx/brams_init.mk
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techlibs/xilinx/brams_init_18.vh: techlibs/xilinx/brams_init.mk
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techlibs/xilinx/brams_init_16.vh: techlibs/xilinx/brams_init.mk
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techlibs/xilinx/brams_init_9.vh: techlibs/xilinx/brams_init.mk
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techlibs/xilinx/brams_init_8.vh: techlibs/xilinx/brams_init.mk
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_cells_xtra.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6v_cells_xtra.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_cells_xtra.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_cells_xtra.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_bb.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_ff_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_ff_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3s_mult_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3sda_dsp_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_dsp_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc4v_dsp_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc5v_dsp_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_dsp_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_dsp_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_unmap.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_model.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_xc7.box))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_xc7.lut))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_xc7_nowide.lut))
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$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
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$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
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$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_18.vh))
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$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_16.vh))
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$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_9.vh))
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$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_8.vh))
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