yosys/techlibs
Marcin Kościelnicki 7b350cacd4 xilinx: Support multiplier mapping for all families.
This supports several older families that are not yet supported for
actual logic synthesis — the intention is to add them soon.
2019-10-22 18:06:57 +02:00
..
achronix Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
anlogic make note that it is for latch mode 2019-09-18 17:48:16 +02:00
common Makefile: don't assume python is called `python3` 2019-10-19 14:04:52 +08:00
coolrunner2 Fix spacing 2019-08-06 16:47:55 -07:00
easic Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
ecp5 ecp5: Pass -nomfs to abc9 2019-10-20 10:30:41 +01:00
efinix FF should be initialized to 0 2019-10-04 13:27:10 +02:00
gowin Fix formatting for msys2 mingw build using GetSize 2019-08-01 17:27:34 +02:00
greenpak4 Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
ice40 Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg 2019-10-22 17:36:54 +02:00
intel techlibs/intel: Clean up Makefile 2019-08-05 11:22:11 -07:00
sf2 Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
xilinx xilinx: Support multiplier mapping for all families. 2019-10-22 18:06:57 +02:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00