mirror of https://github.com/YosysHQ/yosys.git
71 lines
3.0 KiB
Verilog
71 lines
3.0 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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(* blackbox *)
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module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wren_b, rden_b,
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q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1,
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addressstall_a, addressstall_b);
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parameter clock_enable_input_b = "ALTERNATE";
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parameter clock_enable_input_a = "ALTERNATE";
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parameter clock_enable_output_b = "NORMAL";
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parameter clock_enable_output_a = "NORMAL";
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parameter wrcontrol_aclr_a = "NONE";
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parameter indata_aclr_a = "NONE";
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parameter address_aclr_a = "NONE";
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parameter outdata_aclr_a = "NONE";
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parameter outdata_reg_a = "UNREGISTERED";
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parameter operation_mode = "SINGLE_PORT";
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parameter intended_device_family = "MAX 10 FPGA";
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parameter outdata_reg_a = "UNREGISTERED";
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parameter lpm_type = "altsyncram";
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parameter init_type = "unused";
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parameter ram_block_type = "AUTO";
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parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO";
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parameter power_up_uninitialized = "FALSE";
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parameter read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ";
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parameter width_byteena_a = 1;
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parameter numwords_b = 0;
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parameter numwords_a = 0;
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parameter widthad_b = 1;
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parameter width_b = 1;
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parameter widthad_a = 1;
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parameter width_a = 1;
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// Port A declarations
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output [35:0] q_a;
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input [35:0] data_a;
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input [7:0] address_a;
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input wren_a;
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input rden_a;
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// Port B declarations
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output [35:0] q_b;
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input [35:0] data_b;
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input [7:0] address_b;
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input wren_b;
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input rden_b;
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// Control signals
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input clock0, clock1;
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input clocken0, clocken1, clocken2, clocken3;
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input aclr0, aclr1;
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input addressstall_a;
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input addressstall_b;
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// TODO: Implement the correct simulation model
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endmodule // altsyncram
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