yosys/techlibs/anlogic
whitequark efa278e232 Fix typographical and grammatical errors and inconsistencies.
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
..
Makefile.inc anlogic: fix Makefile.inc 2018-12-19 10:23:58 +08:00
anlogic_eqn.cc Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00
arith_map.v Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00
cells_map.v anlogic: add latch cells 2018-12-25 22:47:46 +08:00
cells_sim.v Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00
drams.txt anlogic: fix dbits of Anlogic Eagle DRAM16X4 2018-12-18 14:38:44 +08:00
drams_map.v anlogic: add support for Eagle Distributed RAM 2018-12-17 23:20:40 +08:00
eagle_bb.v Revert "Leave only real black box cells" 2018-12-17 23:20:40 +08:00
synth_anlogic.cc Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00