mirror of https://github.com/YosysHQ/yosys.git
0c318e7db5
The semantics of an RTLIL constant that has less bits than its declared bit width is zero padding. Therefore, if the output of memory_collect will be used for simulation, truncating 'x from the end of \INIT will produce incorrect simulation results. |
||
|---|---|---|
| .. | ||
| cmds | ||
| equiv | ||
| fsm | ||
| hierarchy | ||
| memory | ||
| opt | ||
| proc | ||
| sat | ||
| techmap | ||
| tests | ||