Clifford Wolf 6fe3d5a1cf Added synth_ice40 support for latches via logic loops		2016-05-06 23:02:37 +02:00
..
tests	Initialization support for all iCE40 bram modes	2015-04-26 08:39:31 +02:00
.gitignore	Initialization support for all iCE40 bram modes	2015-04-26 08:39:31 +02:00
Makefile.inc	Added synth_ice40 support for latches via logic loops	2016-05-06 23:02:37 +02:00
arith_map.v	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
brams.txt	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
brams_init.py	Switched to Python 3	2015-08-22 09:59:33 +02:00
brams_map.v	Fixed WE/RE usage in iCE40 BRAM mapping	2015-11-24 10:51:34 +01:00
cells_map.v	improved ice40 dff cell mapping	2015-04-16 11:30:56 +02:00
cells_sim.v	Work around DDR dout sim glitches in ice40 SB_IO sim model	2016-02-07 11:19:48 +01:00
ice40_ffinit.cc	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00
ice40_ffssr.cc	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00
ice40_opt.cc	Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"	2016-05-06 14:32:32 +02:00
latches_map.v	Added synth_ice40 support for latches via logic loops	2016-05-06 23:02:37 +02:00
synth_ice40.cc	Added synth_ice40 support for latches via logic loops	2016-05-06 23:02:37 +02:00