David Shah edff79a25a xilinx: Rework labels for faster Verilator testing ... Signed-off-by: David Shah <dave@ds0.me>		2019-08-13 10:29:42 +01:00
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achronix	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
anlogic	anlogic : Fix alu mapping	2019-08-03 14:47:33 +02:00
common	Merge remote-tracking branch 'origin/master' into xc7dsp	2019-08-12 11:32:10 -07:00
coolrunner2	Fix spacing	2019-08-06 16:47:55 -07:00
easic	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
ecp5	ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinx	2019-08-08 15:18:59 +01:00
gowin	Fix formatting for msys2 mingw build using GetSize	2019-08-01 17:27:34 +02:00
greenpak4	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
ice40	Merge remote-tracking branch 'origin/master' into xc7dsp	2019-08-12 11:32:10 -07:00
intel	Merge branch 'ZirconiumX-synth_intel_m9k'	2019-07-25 17:23:48 +02:00
sf2	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
xilinx	xilinx: Rework labels for faster Verilator testing	2019-08-13 10:29:42 +01:00
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00