yosys/passes
Clifford Wolf f0df7dd796 Added cell port resizing to hierarchy pass 2017-01-01 23:03:44 +01:00
..
cmds Added "design -reset-vlog" 2016-11-30 11:25:55 +01:00
equiv Improved equiv_purge log output 2016-11-29 13:30:35 +01:00
fsm Added support for fsm_encoding="user" 2016-11-02 13:15:49 +01:00
hierarchy Added cell port resizing to hierarchy pass 2017-01-01 23:03:44 +01:00
memory Typo fix. 2016-09-08 10:57:16 +03:00
opt Added opt_rmdff support for $ff cells 2016-10-14 13:02:36 +02:00
proc Added $global_clock verilog syntax support for creating $ff cells 2016-10-14 12:33:56 +02:00
sat Bugfix in "miter -assert" handling of assumptions 2016-10-17 14:56:58 +02:00
techmap Improved ABC default scripts 2016-11-19 18:20:54 +01:00
tests Cosmetic fix in test_autotb.cc 2016-09-19 20:43:43 +02:00